From patchwork Thu Jan 26 22:21:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Kisky X-Patchwork-Id: 138091 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4465B1007D2 for ; Fri, 27 Jan 2012 11:23:22 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 02B91280AB; Fri, 27 Jan 2012 01:23:14 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PgTeAkBBKn35; Fri, 27 Jan 2012 01:23:13 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7D0A22809A; Fri, 27 Jan 2012 01:22:59 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5809E28087 for ; Thu, 26 Jan 2012 23:28:32 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3bwZPGaVh-oR for ; Thu, 26 Jan 2012 23:28:31 +0100 (CET) X-Greylist: delayed 399 seconds by postgrey-1.27 at theia; Thu, 26 Jan 2012 23:28:29 CET X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from oproxy9.bluehost.com (oproxy9.bluehost.com [69.89.24.6]) by theia.denx.de (Postfix) with SMTP id 2B17028089 for ; Thu, 26 Jan 2012 23:28:29 +0100 (CET) Received: (qmail 24398 invoked by uid 0); 26 Jan 2012 22:21:48 -0000 Received: from unknown (HELO box284.bluehost.com) (69.89.31.84) by oproxy9.bluehost.com with SMTP; 26 Jan 2012 22:21:48 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=boundarydevices.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=35asYuXe++DEjcFO6FQlr0snIKeLOk83aUC7H2KtzbU=; b=XQsM+Ls2v8uIqKhQaC61qsDCRIdZFAYk4Hr71zr0Ti1SE8RYbfiTiYcwldfF1uEVC5hmwffP8VGOjmZD2jtWAEOo+lko03ENtVVe9bU3QKIXmSMIJ/vMhpZNTTVnD6WI; Received: from [70.96.116.236] (helo=officeserver-2) by box284.bluehost.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.76) (envelope-from ) id 1RqXhT-0002zp-GH; Thu, 26 Jan 2012 15:21:47 -0700 Received: from tkisky by officeserver-2 with local (Exim 4.76) (envelope-from ) id 1RqXhf-00032u-Sx; Thu, 26 Jan 2012 15:21:59 -0700 From: Troy Kisky To: dirk.behme@googlemail.com Date: Thu, 26 Jan 2012 15:21:45 -0700 Message-Id: <1327616505-11669-4-git-send-email-troy.kisky@boundarydevices.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1327616505-11669-1-git-send-email-troy.kisky@boundarydevices.com> References: <1327616505-11669-1-git-send-email-troy.kisky@boundarydevices.com> X-Identified-User: {1412:box284.bluehost.com:boundar4:boundarydevices.com} {sentby:smtp auth 70.96.116.236 authed with troy.kisky@boundarydevices.com} X-Mailman-Approved-At: Fri, 27 Jan 2012 01:22:52 +0100 Cc: u-boot@lists.denx.de, jason.hui@linaro.org, r49496@freescale.com Subject: [U-Boot] [PATCH 4/4] i.mx6q: mx6qsabrelite: Update the network configuration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Enable the usage of PHY_MICREL_KSZ9021, and minimize the tx clock delay. There is an issue with 1000 baseTx mode on early revs of the SabreLite boards. The center tap pin 9 of the mag RJ45 USB combo was connected to the 3.3 filtered supply. Letting this pin float solved the problem. Symptoms of the problem were packets with many extra zeroes tacked on the end, and random bit flips causing a high rate of CRC errors. 10/100 baseTx worked fine on all revs. To disable 1000 baseTx for these boards, simply define the environment variable disable_giga. ie. setenv disable_giga 1 Signed-off-by: Troy Kisky --- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 43 +----------------------- include/configs/mx6qsabrelite.h | 7 ++++ 2 files changed, 9 insertions(+), 41 deletions(-) diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index e6c12a5..77fb79c 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -187,53 +187,14 @@ int board_mmc_init(bd_t *bis) } #endif -#define MII_1000BASET_CTRL 0x9 -#define MII_EXTENDED_CTRL 0xb -#define MII_EXTENDED_DATAW 0xc - -int fecmxc_mii_postcall(int phy) -{ - /* prefer master mode */ - miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00); - - /* min rx data delay */ - miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105); - miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000); - - /* max rx/tx clock delay, min rx/tx control delay */ - miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104); - miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0); - miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x104); - - return 0; -} - int board_eth_init(bd_t *bis) { - struct eth_device *dev; int ret; - setup_iomux_enet(); - ret = cpu_eth_init(bis); - if (ret) { + if (ret) printf("FEC MXC: %s:failed\n", __func__); - return ret; - } - - dev = eth_get_dev_by_name("FEC"); - if (!dev) { - printf("FEC MXC: Unable to get FEC device entry\n"); - return -EINVAL; - } - - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXC: Unable to register FEC mii postcall\n"); - return ret; - } - - return 0; + return ret; } int board_early_init_f(void) diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 86b25d9..cbae4c3 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -66,6 +66,13 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 6 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL_KSZ9021 +#define CONFIG_PHY_MICREL_KSZ9021_INIT_CMDS \ + 0x8105, 0x0000, /* min rx data delay */ \ + 0x8106, 0x0000, /* min tx data delay */ \ + 0x8104, 0xf0f0, /* max rx/tx clock delay, min rx/tx control */ + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE