From patchwork Wed Sep 21 21:24:21 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 115858 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 7BD4AB6F83 for ; Thu, 22 Sep 2011 07:24:44 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6DCC628323; Wed, 21 Sep 2011 23:24:41 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sthAl2W8jLsY; Wed, 21 Sep 2011 23:24:41 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0CF61281F5; Wed, 21 Sep 2011 23:24:39 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 215C3281F5 for ; Wed, 21 Sep 2011 23:24:37 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Qb9el289JH92 for ; Wed, 21 Sep 2011 23:24:35 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp-out.google.com (smtp-out.google.com [216.239.44.51]) by theia.denx.de (Postfix) with ESMTPS id 9BE5B281AB for ; Wed, 21 Sep 2011 23:24:33 +0200 (CEST) Received: from hpaq7.eem.corp.google.com (hpaq7.eem.corp.google.com [172.25.149.7]) by smtp-out.google.com with ESMTP id p8LLOOqO012667; Wed, 21 Sep 2011 14:24:24 -0700 Received: from sglass.mtv.corp.google.com (sglass.mtv.corp.google.com [172.22.72.144]) by hpaq7.eem.corp.google.com with ESMTP id p8LLOMcf017046; Wed, 21 Sep 2011 14:24:22 -0700 Received: by sglass.mtv.corp.google.com (Postfix, from userid 121222) id E2AB6140742; Wed, 21 Sep 2011 14:24:21 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Wed, 21 Sep 2011 14:24:21 -0700 Message-Id: <1316640261-5152-1-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.3.1 X-System-Of-Record: true Cc: Tom Warren Subject: [U-Boot] [PATCH v2] tegra2: Enable data cache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This enables the data cache on Tegra2 boards. As discussed on the list, this is better off in the Tegra2 cpu code than in a particular vendor directory. We should be safe turning on the cache for all Tegra2 boards. Signed-off-by: Simon Glass --- Changes in v2: - Enable caches for all Tegra2 boards instead of just Nvidia ones arch/arm/cpu/armv7/tegra2/board.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index 9061d18..a996b88 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -86,3 +86,11 @@ int checkboard(void) return 0; } #endif /* CONFIG_DISPLAY_BOARDINFO */ + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif