From patchwork Fri Aug 5 04:44:12 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xu, Hong" X-Patchwork-Id: 108607 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1C7A8B6F76 for ; Fri, 5 Aug 2011 14:45:46 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7C9AB2810B; Fri, 5 Aug 2011 06:45:41 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CvEo47iCN1BU; Fri, 5 Aug 2011 06:45:41 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 98EA02817A; Fri, 5 Aug 2011 06:45:38 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3FF7B2817A for ; Fri, 5 Aug 2011 06:45:33 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bgVXf9enyafi for ; Fri, 5 Aug 2011 06:45:28 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from sjogate2.atmel.com (newsmtp5.atmel.com [204.2.163.5]) by theia.denx.de (Postfix) with ESMTP id 6425B2810B for ; Fri, 5 Aug 2011 06:45:26 +0200 (CEST) Received: from localhost.localdomain ([10.217.2.49]) by sjogate2.atmel.com (8.13.6/8.13.6) with ESMTP id p754fsOW023828; Thu, 4 Aug 2011 21:42:04 -0700 (PDT) From: Hong Xu To: u-boot@lists.denx.de Date: Fri, 5 Aug 2011 12:44:12 +0800 Message-Id: <1312519452-22926-1-git-send-email-hong.xu@atmel.com> X-Mailer: git-send-email 1.7.3.3 Cc: albert.aribaud@free.fr, hs@denx.de Subject: [U-Boot] [PATCH v2] ARM926ejs: Add routines to invalidate D-Cache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de After DMA operation, we need to maintain D-Cache coherency. We need to clean cache (write back the dirty lines) and then make the cache invalidate as well(hence CPU will fetch data written by DMA controller from RAM). Tested on AT91SAM9261EK with Peripheral DMA controller. Signed-off-by: Hong Xu Tested-by: Elen Song CC: Albert Aribaud CC: Heiko Schocher --- Changes since v1 ~ Per Albert's suggestion, add invalidate_dcache_range originally defined in include/common.h arch/arm/lib/cache.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 46 insertions(+), 0 deletions(-) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 92b61a2..0436443 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -53,3 +53,49 @@ void __flush_dcache_all(void) } void flush_dcache_all(void) __attribute__((weak, alias("__flush_dcache_all"))); + +void __invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + int cache_line_len; + unsigned long mva; + +#ifdef CONFIG_ARM926EJS + +#ifdef CONFIG_SYS_CACHELINE_SIZE + cache_line_len = CONFIG_SYS_CACHELINE_SIZE; +#else + cache_line_len = 32; +#endif + /* + * If start and stop are not aligned to cache-line, + * the adjacent lines will be cleaned + */ + if ((start & (cache_line_len - 1)) != 0) + asm("mcr p15, 0, %0, c7, c10, 1" : : "r" (start)); + if ((stop & (cache_line_len - 1)) != 0) + asm("mcr p15, 0, %0, c7, c10, 1" : : "r" (stop)); + + mva = start & ~(cache_line_len - 1); + while (mva < stop) { + asm("mcr p15, 0, %0, c7, c6, 1" : : "r"(mva)); + mva += cache_line_len; + } + + /* Drain the WB */ + asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); +#endif + + return; +} +void invalidate_dcache_range(unsigned long start, unsigned long stop) + __attribute__((weak, alias("__invalidate_dcache_range"))); + +void __invalidate_dcache_all(void) +{ +#ifdef CONFIG_ARM926EJS + asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); +#endif + return; +} +void invalidate_dcache_all(void) + __attribute__((weak, alias("__invalidate_dcache_all")));