Message ID | 1312452625-11060-3-git-send-email-thomas.petazzoni@free-electrons.com |
---|---|
State | Changes Requested |
Delegated to: | Reinhard Meyer |
Headers | show |
Dear Thomas Petazzoni, > Based on earlier work by Alex Waterman <awaterman@dawning.com>. > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > --- > Makefile | 21 --- > board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 121 +++++++++------- > board/atmel/at91sam9m10g45ek/led.c | 6 +- > boards.cfg | 1 + > include/configs/at91sam9m10g45ek.h | 187 +++++++++++------------ > 5 files changed, 160 insertions(+), 176 deletions(-) > First, the checkpatch complaints: WARNING: Use #include <linux/io.h> instead of <asm/io.h> #67: FILE: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c:26: +#include <asm/io.h> --> ignore this ERROR: "(foo*)" should be "(foo *)" #284: FILE: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c:291: + gd->ram_size = get_ram_size((void*) CONFIG_SYS_SDRAM_BASE, WARNING: externs should be avoided in .c files #303: FILE: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c:347: +extern void at91_serial_hw_init(void); --> you need to call at91_seriald_hw_init() anyway! WARNING: Use #include <linux/io.h> instead of <asm/io.h> #322: FILE: board/atmel/at91sam9m10g45ek/led.c:26: +#include <asm/io.h> --> ignore this WARNING: please, no space for starting a line, excluding comments #498: FILE: include/configs/at91sam9m10g45ek.h:128: + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)$ total: 1 errors, 4 warnings, 550 lines checked U-Boot-2-2-atmel-Update-support-of-board-AT91SAM9M10G45-EK-to-new-style.patch has style problems, please review. > diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c > index f92b20f..40ee345 100644 > --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c > +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c > @@ -23,17 +23,14 @@ > */ > > #include <common.h> > -#include <asm/sizes.h> > -#include <asm/arch/at91sam9g45.h> > -#include <asm/arch/at91sam9_matrix.h> > +#include <asm/io.h> > +#include <asm/arch/at91sam9g45_matrix.h> > #include <asm/arch/at91sam9_smc.h> > #include <asm/arch/at91_common.h> > #include <asm/arch/at91_pmc.h> > #include <asm/arch/at91_rstc.h> > -#include <asm/arch/clk.h> > #include <asm/arch/gpio.h> > -#include <asm/arch/io.h> > -#include <asm/arch/hardware.h> > +#include <asm/arch/clk.h> > #include <lcd.h> > #include <atmel_lcdc.h> > #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) > @@ -49,35 +46,38 @@ DECLARE_GLOBAL_DATA_PTR; > */ > > #ifdef CONFIG_CMD_NAND > -static void at91sam9m10g45ek_nand_hw_init(void) > +void at91sam9m10g45ek_nand_hw_init(void) > { > + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; > + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; > + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > unsigned long csa; > > /* Enable CS3 */ > - csa = at91_sys_read(AT91_MATRIX_EBICSA); > - at91_sys_write(AT91_MATRIX_EBICSA, > - csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); > + csa = readl(&matrix->ebicsa); > + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; > + writel(csa, &matrix->ebicsa); > > /* Configure SMC CS3 for NAND/SmartMedia */ > - at91_sys_write(AT91_SMC_SETUP(3), > - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | > - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); > - at91_sys_write(AT91_SMC_PULSE(3), > - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) | > - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2)); > - at91_sys_write(AT91_SMC_CYCLE(3), > - AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4)); > - at91_sys_write(AT91_SMC_MODE(3), > - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | > - AT91_SMC_EXNWMODE_DISABLE | > + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | > + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), > + &smc->cs[3].setup); > + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | > + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), > + &smc->cs[3].pulse); > + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), > + &smc->cs[3].cycle); > + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | > + AT91_SMC_MODE_EXNW_DISABLE | > #ifdef CONFIG_SYS_NAND_DBW_16 > - AT91_SMC_DBW_16 | > + AT91_SMC_MODE_DBW_16 | > #else /* CONFIG_SYS_NAND_DBW_8 */ > - AT91_SMC_DBW_8 | > + AT91_SMC_MODE_DBW_8 | > #endif > - AT91_SMC_TDF_(3)); > + AT91_SMC_MODE_TDF_CYCLE(3), > + &smc->cs[3].mode); > > - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC); > + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); > > /* Configure RDY/BSY */ > at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); > @@ -90,7 +90,9 @@ static void at91sam9m10g45ek_nand_hw_init(void) > #ifdef CONFIG_CMD_USB > static void at91sam9m10g45ek_usb_hw_init(void) > { > - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE); > + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > + > + writel(1 << ATMEL_ID_PIODE, &pmc->pcer); > > at91_set_gpio_output(AT91_PIN_PD1, 0); > at91_set_gpio_output(AT91_PIN_PD3, 0); > @@ -100,47 +102,50 @@ static void at91sam9m10g45ek_usb_hw_init(void) > #ifdef CONFIG_MACB > static void at91sam9m10g45ek_macb_hw_init(void) > { > - unsigned long rstc; > + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; > + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; > + unsigned long erstl; > > /* Enable clock */ > - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC); > + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); > > /* > * Disable pull-up on: > - * RXDV (PA15) => PHY normal mode (not Test mode) > - * ERX0 (PA12) => PHY ADDR0 > - * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 > + * RXDV (PA15) => PHY normal mode (not Test mode) > + * ERX0 (PA12) => PHY ADDR0 > + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 > * > * PHY has internal pull-down > */ > writel(pin_to_mask(AT91_PIN_PA15) | > pin_to_mask(AT91_PIN_PA12) | > pin_to_mask(AT91_PIN_PA13), > - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); > + &pioa->pudr); > > - rstc = at91_sys_read(AT91_RSTC_MR); > + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; > > /* Need to reset PHY -> 500ms reset */ > - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | > - (AT91_RSTC_ERSTL & (0x0D << 8)) | > - AT91_RSTC_URSTEN); > + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | > + AT91_RSTC_MR_URSTEN, &rstc->mr); > > - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); > + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); > > /* Wait for end hardware reset */ > - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); > + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) > + ; > > /* Restore NRST value */ > - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | > - (rstc) | > - AT91_RSTC_URSTEN); > + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, > + &rstc->mr); > > /* Re-enable pull-up */ > writel(pin_to_mask(AT91_PIN_PA15) | > pin_to_mask(AT91_PIN_PA12) | > pin_to_mask(AT91_PIN_PA13), > - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); > + &pioa->puer); > > + /* And the pins. */ > at91_macb_hw_init(); > } > #endif > @@ -161,7 +166,7 @@ vidinfo_t panel_info = { > vl_vsync_len: 1, > vl_upper_margin:40, > vl_lower_margin:1, > - mmio: AT91SAM9G45_LCDC_BASE, > + mmio : ATMEL_BASE_LCDC, > }; > > > @@ -177,6 +182,8 @@ void lcd_disable(void) > > static void at91sam9m10g45ek_lcd_hw_init(void) > { > + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > + > at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ > at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ > at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ > @@ -208,7 +215,7 @@ static void at91sam9m10g45ek_lcd_hw_init(void) > at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ > at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ > > - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC); > + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); > > gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; > } > @@ -227,7 +234,7 @@ void lcd_show_board_info(void) > lcd_printf ("(C) 2008 ATMEL Corp\n"); > lcd_printf ("at91support@atmel.com\n"); > lcd_printf ("%s CPU at %s MHz\n", > - CONFIG_SYS_AT91_CPU_NAME, > + ATMEL_CPU_NAME, > strmhz(temp, get_cpu_clk_rate())); > > dram_size = 0; > @@ -254,10 +261,10 @@ int board_init(void) > #elif defined CONFIG_AT91SAM9G45EKES > gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES; > #endif > + > /* adress of boot parameters */ > - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; > + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; > > - at91_serial_hw_init(); > #ifdef CONFIG_CMD_NAND > at91sam9m10g45ek_nand_hw_init(); > #endif > @@ -270,11 +277,9 @@ int board_init(void) > #ifdef CONFIG_ATMEL_SPI > at91_spi0_hw_init(1 << 4); > #endif > - > #ifdef CONFIG_MACB > at91sam9m10g45ek_macb_hw_init(); > #endif > - > #ifdef CONFIG_LCD > at91sam9m10g45ek_lcd_hw_init(); > #endif > @@ -283,8 +288,8 @@ int board_init(void) > > int dram_init(void) > { > - gd->bd->bi_dram[0].start = PHYS_SDRAM; > - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; > + gd->ram_size = get_ram_size((void*) CONFIG_SYS_SDRAM_BASE, > + CONFIG_SYS_SDRAM_SIZE); > return 0; > } > > @@ -298,7 +303,7 @@ int board_eth_init(bd_t *bis) > { > int rc = 0; > #ifdef CONFIG_MACB > - rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00); > + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); > #endif > return rc; > } > @@ -338,3 +343,15 @@ void spi_cs_deactivate(struct spi_slave *slave) > } > } > #endif /* CONFIG_ATMEL_SPI */ > + > +extern void at91_serial_hw_init(void); > +/* > + * (re)Initialize the serial hardware. > + */ > +int board_early_init_f(void) > +{ > + > + at91_serial_hw_init(); --> *seriald* > + return 0; > + > +} > diff --git a/boards.cfg b/boards.cfg > index 38ccb8c..9dd313b 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -96,6 +96,7 @@ at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel > at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH > at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 > at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 > +at91sam9m10g45ek_nandflash arm arm926ejs at91sam9m10g45ek atmel at91 at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH "m" comes before "x" - and the indentation seems off by one space > snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 > snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 > cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260 > diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h > index de74dcf..384a07c 100644 > --- a/include/configs/at91sam9m10g45ek.h > +++ b/include/configs/at91sam9m10g45ek.h > @@ -27,48 +27,64 @@ > #ifndef __CONFIG_H > #define __CONFIG_H > > +#include <asm/hardware.h> > + > #define CONFIG_AT91_LEGACY > +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ > > /* ARM asynchronous clock */ > -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ > -#define CONFIG_SYS_HZ 1000 > - > -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ > -#ifdef CONFIG_AT91SAM9M10G45EK > -#define CONFIG_AT91SAM9M10G45 1 /* It's an Atmel AT91SAM9M10G45 SoC*/ > -#else > -#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC*/ > -#endif > +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 > +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ > +#define CONFIG_SYS_HZ 1000 > + > +#define CONFIG_AT91SAM9M10G45EK > +#define CONFIG_AT91FAMILY > #define CONFIG_ARCH_CPU_INIT > +#define CONFIG_BOARD_EARLY_INIT_F > #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ > > -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ > -#define CONFIG_SETUP_MEMORY_TAGS 1 > -#define CONFIG_INITRD_TAG 1 > +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ > +#define CONFIG_SETUP_MEMORY_TAGS > +#define CONFIG_INITRD_TAG > > #define CONFIG_SKIP_LOWLEVEL_INIT > > +#define ATMEL_PIO_PORTS 5 /* 5 PIO ports. */ THAT does not belong here. It should be in at91sam9m10g45.h > + > /* > * Hardware drivers > */ > -#define CONFIG_AT91_GPIO 1 > -#define CONFIG_ATMEL_USART 1 > +#define CONFIG_AT91_GPIO > +#define CONFIG_ATMEL_USART > #undef CONFIG_USART0 > #undef CONFIG_USART1 > #undef CONFIG_USART2 > -#define CONFIG_USART3 1 /* USART 3 is DBGU */ > +#define CONFIG_USART3 /* USART 3 is DBGU */ Nope. This is wrong. See other 926x boards! > +#define CONFIG_USART_BASE 0xffffee00 /* Use the DBGU hardware. */ > +#define CONFIG_USART_ID 10 OUCH. There are defines for that in at91sam9m10g45.h > + > +/* > + * This needs to be defined for the OHCI code to work but it is defined as > + * ATMEL_ID_UHPHS in the CPU specific header files. > + */ > +#define ATMEL_ID_UHP ATMEL_ID_UHPHS > + > +/* > + * Specify the clock enable bit in the PMC_SCER register. > + */ > +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP > > /* LCD */ > -#define CONFIG_LCD 1 > +#define CONFIG_LCD > #define LCD_BPP LCD_COLOR8 > -#define CONFIG_LCD_LOGO 1 > +#define CONFIG_LCD_LOGO > #undef LCD_TEST_PATTERN > -#define CONFIG_LCD_INFO 1 > -#define CONFIG_LCD_INFO_BELOW_LOGO 1 > -#define CONFIG_SYS_WHITE_ON_BLACK 1 > -#define CONFIG_ATMEL_LCD 1 > -#define CONFIG_ATMEL_LCD_RGB565 1 > -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 > +#define CONFIG_LCD_INFO > +#define CONFIG_LCD_INFO_BELOW_LOGO > +#define CONFIG_SYS_WHITE_ON_BLACK > +#define CONFIG_ATMEL_LCD > +#define CONFIG_ATMEL_LCD_RGB565 > +#define CONFIG_SYS_CONSOLE_IS_IN_ENV > /* board specific(not enough SRAM) */ > #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000 > > @@ -82,10 +98,10 @@ > /* > * BOOTP options > */ > -#define CONFIG_BOOTP_BOOTFILESIZE 1 > -#define CONFIG_BOOTP_BOOTPATH 1 > -#define CONFIG_BOOTP_GATEWAY 1 > -#define CONFIG_BOOTP_HOSTNAME 1 > +#define CONFIG_BOOTP_BOOTFILESIZE > +#define CONFIG_BOOTP_BOOTPATH > +#define CONFIG_BOOTP_GATEWAY > +#define CONFIG_BOOTP_HOSTNAME > > /* > * Command line configuration. > @@ -98,44 +114,29 @@ > #undef CONFIG_CMD_AUTOSCRIPT > #undef CONFIG_CMD_LOADS > > -#define CONFIG_CMD_PING 1 > -#define CONFIG_CMD_DHCP 1 > -#define CONFIG_CMD_NAND 1 > -#define CONFIG_CMD_USB 1 > +#define CONFIG_CMD_PING > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_NAND > +#define CONFIG_CMD_USB > > /* SDRAM */ > #define CONFIG_NR_DRAM_BANKS 1 > -#define PHYS_SDRAM 0x70000000 > -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ > - > -/* DataFlash */ > -#ifdef CONFIG_ATMEL_SPI > -#define CONFIG_CMD_SF > -#define CONFIG_CMD_SPI > -#define CONFIG_SPI_FLASH 1 > -#define CONFIG_SPI_FLASH_ATMEL 1 > -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 > -#endif > +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 > +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 > > -/* NOR flash, if populated */ > -#ifndef CONFIG_CMD_NAND > -#define CONFIG_SYS_NO_FLASH 1 > -#else > -#define CONFIG_SYS_FLASH_CFI 1 > -#define CONFIG_FLASH_CFI_DRIVER 1 > -#define PHYS_FLASH_1 0x10000000 > -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 > -#define CONFIG_SYS_MAX_FLASH_SECT 256 > -#define CONFIG_SYS_MAX_FLASH_BANKS 1 > -#endif > +#define CONFIG_SYS_INIT_SP_ADDR \ > + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) > + > +/* No NOR flash */ > +#define CONFIG_SYS_NO_FLASH > > /* NAND flash */ > #ifdef CONFIG_CMD_NAND > #define CONFIG_NAND_MAX_CHIPS 1 > #define CONFIG_NAND_ATMEL > #define CONFIG_SYS_MAX_NAND_DEVICE 1 > -#define CONFIG_SYS_NAND_BASE 0x40000000 > -#define CONFIG_SYS_NAND_DBW_8 1 > +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 > +#define CONFIG_SYS_NAND_DBW_8 > /* our ALE is AD21 */ > #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) > /* our CLE is AD22 */ > @@ -146,68 +147,52 @@ > #endif > > /* Ethernet */ > -#define CONFIG_MACB 1 > -#define CONFIG_RMII 1 > -#define CONFIG_NET_MULTI 1 > +#define CONFIG_MACB > +#define CONFIG_RMII > +#define CONFIG_NET_MULTI > #define CONFIG_NET_RETRY_COUNT 20 > -#define CONFIG_RESET_PHY_R 1 > +#define CONFIG_RESET_PHY_R > > /* USB */ > #define CONFIG_USB_ATMEL > -#define CONFIG_USB_OHCI_NEW 1 > -#define CONFIG_DOS_PARTITION 1 > -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 > -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91SAM9G45_UHP_OHCI_BASE */ > -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" > +#define CONFIG_USB_OHCI_NEW > +#define CONFIG_DOS_PARTITION > +#define CONFIG_SYS_USB_OHCI_CPU_INIT > +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_HCI > +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" > #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 > -#define CONFIG_USB_STORAGE 1 > - > -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ > - > -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM > -#define CONFIG_SYS_MEMTEST_END 0x23e00000 > +#define CONFIG_USB_STORAGE > > -#ifdef CONFIG_SYS_USE_DATAFLASH > +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ > > -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ > -#define CONFIG_ENV_IS_IN_SPI_FLASH 1 > -#define CONFIG_SYS_MONITOR_BASE (0xC0000000 + 0x8400) > -#define CONFIG_ENV_OFFSET 0x4200 > -#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET) > -#define CONFIG_ENV_SIZE 0x4200 > -#define CONFIG_ENV_SECT_SIZE 0x10000 > -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" > -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ > - "root=/dev/mtdblock0 " \ > - "mtdparts=atmel_nand:-(root) "\ > - "rw rootfstype=jffs2" > +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE > +#define CONFIG_SYS_MEMTEST_END 0x23e00000 > > -#else /* CONFIG_SYS_USE_NANDFLASH */ > - > -/* bootstrap + u-boot + env + linux in nandflash */ > -#define CONFIG_ENV_IS_IN_NAND 1 > +/* bootstrap + u-boot + env in nandflash */ > +#define CONFIG_ENV_IS_IN_NAND > #define CONFIG_ENV_OFFSET 0x60000 > #define CONFIG_ENV_OFFSET_REDUND 0x80000 > -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ > -#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" > -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ > - "root=/dev/mtdblock5 " \ > - "mtdparts=atmel_nand:128k(bootstrap)ro, \ > - 256k(uboot)ro,128k(env1)ro,128k(env2)ro, \ > - 2M(linux),-(root) " \ > - "rw rootfstype=jffs2" > - > -#endif > - > -#define CONFIG_BAUDRATE 115200 > +#define CONFIG_ENV_SIZE 0x20000 > + > +#define CONFIG_BOOTCOMMAND "nand read 0x70000000 0x100000 0x200000;" \ > + "bootm 0x70000000" > +#define CONFIG_BOOTARGS \ > + "console=ttyS0,115200 earlyprintk " \ > + "root=/dev/mtdblock5 " \ > + "mtdparts=atmel_nand:128k(bootstrap)ro," \ > + "256k(uboot)ro,128k(env1)ro,128k(env2)ro," \ > + "2M@1M(linux),-(root) " \ > + "rw rootfstype=jffs2" > + > +#define CONFIG_BAUDRATE 115200 > #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } > > #define CONFIG_SYS_PROMPT "U-Boot> " > #define CONFIG_SYS_CBSIZE 256 > #define CONFIG_SYS_MAXARGS 16 > #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) > -#define CONFIG_SYS_LONGHELP 1 > -#define CONFIG_CMDLINE_EDITING 1 > +#define CONFIG_SYS_LONGHELP > +#define CONFIG_CMDLINE_EDITING > #define CONFIG_AUTO_COMPLETE > #define CONFIG_SYS_HUSH_PARSER > #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " Best Regards, Reinhard
diff --git a/Makefile b/Makefile index 156b21b..7ff3bda 100644 --- a/Makefile +++ b/Makefile @@ -802,27 +802,6 @@ M5485HFE_config : unconfig ## ARM926EJ-S Systems ######################################################################### -at91sam9m10g45ek_nandflash_config \ -at91sam9m10g45ek_dataflash_config \ -at91sam9m10g45ek_dataflash_cs0_config \ -at91sam9m10g45ek_config \ -at91sam9g45ekes_nandflash_config \ -at91sam9g45ekes_dataflash_config \ -at91sam9g45ekes_dataflash_cs0_config \ -at91sam9g45ekes_config : unconfig - @mkdir -p $(obj)include - @if [ "$(findstring 9m10,$@)" ] ; then \ - echo "#define CONFIG_AT91SAM9M10G45EK 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_AT91SAM9G45EKES 1" >>$(obj)include/config.h ; \ - fi; - @if [ "$(findstring _nandflash,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_ATMEL_SPI 1" >>$(obj)include/config.h ; \ - fi; - @$(MKCONFIG) -n $@ -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91 - pm9g45_config : unconfig @mkdir -p $(obj)include @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91 diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index f92b20f..40ee345 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -23,17 +23,14 @@ */ #include <common.h> -#include <asm/sizes.h> -#include <asm/arch/at91sam9g45.h> -#include <asm/arch/at91sam9_matrix.h> +#include <asm/io.h> +#include <asm/arch/at91sam9g45_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> -#include <asm/arch/clk.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> -#include <asm/arch/hardware.h> +#include <asm/arch/clk.h> #include <lcd.h> #include <atmel_lcdc.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) @@ -49,35 +46,38 @@ DECLARE_GLOBAL_DATA_PTR; */ #ifdef CONFIG_CMD_NAND -static void at91sam9m10g45ek_nand_hw_init(void) +void at91sam9m10g45ek_nand_hw_init(void) { + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(3)); + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -90,7 +90,9 @@ static void at91sam9m10g45ek_nand_hw_init(void) #ifdef CONFIG_CMD_USB static void at91sam9m10g45ek_usb_hw_init(void) { - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE); + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(1 << ATMEL_ID_PIODE, &pmc->pcer); at91_set_gpio_output(AT91_PIN_PD1, 0); at91_set_gpio_output(AT91_PIN_PD3, 0); @@ -100,47 +102,50 @@ static void at91sam9m10g45ek_usb_hw_init(void) #ifdef CONFIG_MACB static void at91sam9m10g45ek_macb_hw_init(void) { - unsigned long rstc; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); /* * Disable pull-up on: - * RXDV (PA15) => PHY normal mode (not Test mode) - * ERX0 (PA12) => PHY ADDR0 - * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 + * RXDV (PA15) => PHY normal mode (not Test mode) + * ERX0 (PA12) => PHY ADDR0 + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 * * PHY has internal pull-down */ writel(pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA12) | pin_to_mask(AT91_PIN_PA13), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + &pioa->pudr); - rstc = at91_sys_read(AT91_RSTC_MR); + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0D << 8)) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | + AT91_RSTC_MR_URSTEN, &rstc->mr); - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, + &rstc->mr); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA12) | pin_to_mask(AT91_PIN_PA13), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + &pioa->puer); + /* And the pins. */ at91_macb_hw_init(); } #endif @@ -161,7 +166,7 @@ vidinfo_t panel_info = { vl_vsync_len: 1, vl_upper_margin:40, vl_lower_margin:1, - mmio: AT91SAM9G45_LCDC_BASE, + mmio : ATMEL_BASE_LCDC, }; @@ -177,6 +182,8 @@ void lcd_disable(void) static void at91sam9m10g45ek_lcd_hw_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ @@ -208,7 +215,7 @@ static void at91sam9m10g45ek_lcd_hw_init(void) at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC); + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; } @@ -227,7 +234,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - CONFIG_SYS_AT91_CPU_NAME, + ATMEL_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; @@ -254,10 +261,10 @@ int board_init(void) #elif defined CONFIG_AT91SAM9G45EKES gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES; #endif + /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9m10g45ek_nand_hw_init(); #endif @@ -270,11 +277,9 @@ int board_init(void) #ifdef CONFIG_ATMEL_SPI at91_spi0_hw_init(1 << 4); #endif - #ifdef CONFIG_MACB at91sam9m10g45ek_macb_hw_init(); #endif - #ifdef CONFIG_LCD at91sam9m10g45ek_lcd_hw_init(); #endif @@ -283,8 +288,8 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size((void*) CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -298,7 +303,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); #endif return rc; } @@ -338,3 +343,15 @@ void spi_cs_deactivate(struct spi_slave *slave) } } #endif /* CONFIG_ATMEL_SPI */ + +extern void at91_serial_hw_init(void); +/* + * (re)Initialize the serial hardware. + */ +int board_early_init_f(void) +{ + + at91_serial_hw_init(); + return 0; + +} diff --git a/board/atmel/at91sam9m10g45ek/led.c b/board/atmel/at91sam9m10g45ek/led.c index ff59a2d..dadbd6a 100644 --- a/board/atmel/at91sam9m10g45ek/led.c +++ b/board/atmel/at91sam9m10g45ek/led.c @@ -23,15 +23,17 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/at91sam9g45.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> void coloured_LED_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE); + writel(1 << ATMEL_ID_PIODE, &pmc->pcer); at91_set_gpio_output(CONFIG_RED_LED, 1); at91_set_gpio_output(CONFIG_GREEN_LED, 1); diff --git a/boards.cfg b/boards.cfg index 38ccb8c..9dd313b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -96,6 +96,7 @@ at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 +at91sam9m10g45ek_nandflash arm arm926ejs at91sam9m10g45ek atmel at91 at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260 diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index de74dcf..384a07c 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -27,48 +27,64 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/hardware.h> + #define CONFIG_AT91_LEGACY +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#ifdef CONFIG_AT91SAM9M10G45EK -#define CONFIG_AT91SAM9M10G45 1 /* It's an Atmel AT91SAM9M10G45 SoC*/ -#else -#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC*/ -#endif +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_AT91SAM9M10G45EK +#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT +#define CONFIG_BOARD_EARLY_INIT_F #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT +#define ATMEL_PIO_PORTS 5 /* 5 PIO ports. */ + /* * Hardware drivers */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 +#define CONFIG_AT91_GPIO +#define CONFIG_ATMEL_USART #undef CONFIG_USART0 #undef CONFIG_USART1 #undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_USART3 /* USART 3 is DBGU */ +#define CONFIG_USART_BASE 0xffffee00 /* Use the DBGU hardware. */ +#define CONFIG_USART_ID 10 + +/* + * This needs to be defined for the OHCI code to work but it is defined as + * ATMEL_ID_UHPHS in the CPU specific header files. + */ +#define ATMEL_ID_UHP ATMEL_ID_UHPHS + +/* + * Specify the clock enable bit in the PMC_SCER register. + */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP /* LCD */ -#define CONFIG_LCD 1 +#define CONFIG_LCD #define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 +#define CONFIG_LCD_LOGO #undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_SYS_WHITE_ON_BLACK 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_ATMEL_LCD_RGB565 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_LCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* board specific(not enough SRAM) */ #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000 @@ -82,10 +98,10 @@ /* * BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. @@ -98,44 +114,29 @@ #undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_LOADS -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x70000000 -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ - -/* DataFlash */ -#ifdef CONFIG_ATMEL_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH 1 -#define CONFIG_SPI_FLASH_ATMEL 1 -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 -#endif +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 -/* NOR flash, if populated */ -#ifndef CONFIG_CMD_NAND -#define CONFIG_SYS_NO_FLASH 1 -#else -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#endif +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_MAX_CHIPS 1 #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ @@ -146,68 +147,52 @@ #endif /* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI #define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R 1 +#define CONFIG_RESET_PHY_R /* USB */ #define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91SAM9G45_UHP_OHCI_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_HCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE 1 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END 0x23e00000 +#define CONFIG_USB_STORAGE -#ifdef CONFIG_SYS_USE_DATAFLASH +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_ENV_IS_IN_SPI_FLASH 1 -#define CONFIG_SYS_MONITOR_BASE (0xC0000000 + 0x8400) -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock0 " \ - "mtdparts=atmel_nand:-(root) "\ - "rw rootfstype=jffs2" +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x23e00000 -#else /* CONFIG_SYS_USE_NANDFLASH */ - -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_IS_IN_NAND 1 +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x60000 #define CONFIG_ENV_OFFSET_REDUND 0x80000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock5 " \ - "mtdparts=atmel_nand:128k(bootstrap)ro, \ - 256k(uboot)ro,128k(env1)ro,128k(env2)ro, \ - 2M(linux),-(root) " \ - "rw rootfstype=jffs2" - -#endif - -#define CONFIG_BAUDRATE 115200 +#define CONFIG_ENV_SIZE 0x20000 + +#define CONFIG_BOOTCOMMAND "nand read 0x70000000 0x100000 0x200000;" \ + "bootm 0x70000000" +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "root=/dev/mtdblock5 " \ + "mtdparts=atmel_nand:128k(bootstrap)ro," \ + "256k(uboot)ro,128k(env1)ro,128k(env2)ro," \ + "2M@1M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Based on earlier work by Alex Waterman <awaterman@dawning.com>. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- Makefile | 21 --- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 121 +++++++++------- board/atmel/at91sam9m10g45ek/led.c | 6 +- boards.cfg | 1 + include/configs/at91sam9m10g45ek.h | 187 +++++++++++------------ 5 files changed, 160 insertions(+), 176 deletions(-)