From patchwork Thu Aug 4 03:45:50 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xu, Hong" X-Patchwork-Id: 108342 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 201DAB6F64 for ; Thu, 4 Aug 2011 13:46:23 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1E00428089; Thu, 4 Aug 2011 05:46:19 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Bya7-gzjuWeD; Thu, 4 Aug 2011 05:46:18 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AB2ED2808A; Thu, 4 Aug 2011 05:46:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3ED042808A for ; Thu, 4 Aug 2011 05:46:13 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fDbDst9bwSdz for ; Thu, 4 Aug 2011 05:46:11 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from sjogate2.atmel.com (newsmtp5.atmel.com [204.2.163.5]) by theia.denx.de (Postfix) with ESMTP id 0262F28089 for ; Thu, 4 Aug 2011 05:46:09 +0200 (CEST) Received: from localhost.localdomain ([10.217.2.49]) by sjogate2.atmel.com (8.13.6/8.13.6) with ESMTP id p743gbjV001402; Wed, 3 Aug 2011 20:42:46 -0700 (PDT) From: Hong Xu To: u-boot@lists.denx.de Date: Thu, 4 Aug 2011 11:45:50 +0800 Message-Id: <1312429550-14394-1-git-send-email-hong.xu@atmel.com> X-Mailer: git-send-email 1.7.3.3 Cc: albert.aribaud@free.fr, hs@denx.de Subject: [U-Boot] [PATCH] ARM926ejs: Add routines to invalidate D-Cache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de After DMA transfer, we need to maintain D-Cache coherency. We need to clean cache (write back the dirty lines) and then make the cache invalidate as well(hence CPU will fetch data written by DMA controller from RAM). Tested on AT91SAM9261EK with Peripheral DMA controller. Signed-off-by: Hong Xu Tested-by: Elen Song CC: Heiko Schocher CC: Albert Aribaud --- arch/arm/lib/cache.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 92b61a2..216bde0 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -53,3 +53,13 @@ void __flush_dcache_all(void) } void flush_dcache_all(void) __attribute__((weak, alias("__flush_dcache_all"))); + +void __invalidate_dcache_all(void) +{ +#ifdef CONFIG_ARM926EJS + asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); +#endif + return; +} +void invalidate_dcache_all(void) + __attribute__((weak, alias("__invalidate_dcache_all")));