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[U-Boot,IXP42x,series,v5,15/17] update/fix PDNB3 board

Message ID 1306101613-18200-16-git-send-email-michael@schwingen.org
State Accepted
Headers show

Commit Message

Michael Schwingen May 22, 2011, 10 p.m. UTC 
Signed-off-by: Michael Schwingen <michael@schwingen.org>
---
Changes for V3:
 - new in V3 (split from "update_fix some more IXP42x boards" in V2)
Changes for V4:
 - add changelog
Changes for V5:

 board/prodrive/pdnb3/config.mk |    2 --
 include/configs/pdnb3.h        |   10 +++++++---
 2 files changed, 7 insertions(+), 5 deletions(-)
 delete mode 100644 board/prodrive/pdnb3/config.mk
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Patch

diff --git a/board/prodrive/pdnb3/config.mk b/board/prodrive/pdnb3/config.mk
deleted file mode 100644
index 817541f..0000000
--- a/board/prodrive/pdnb3/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@ 
-#
-CONFIG_SYS_TEXT_BASE = 0x01f00000
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index 33fa6ee..7fe9e5b 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -50,9 +50,6 @@ 
 /*
  * Misc configuration options
  */
-#define CONFIG_USE_IRQ          1	/* we need IRQ stuff for timer	*/
-#define CONFIG_TIMER_IRQ
-
 #define CONFIG_BOOTCOUNT_LIMIT		/* support for bootcount limit	*/
 #define CONFIG_SYS_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
 
@@ -117,6 +114,7 @@ 
 #define CONFIG_SYS_MEMTEST_END         0x00800000      /* 4 ... 8 MB in DRAM   */
 #define CONFIG_SYS_LOAD_ADDR           0x00010000      /* default load address */
 
+#define CONFIG_IXP425_TIMER_CLK		66666666
 #define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
 						/* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
@@ -188,6 +186,7 @@ 
 #define PHYS_SDRAM_1            0x00000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE       0x02000000 /* 32 MB */
 
+#define CONFIG_SYS_TEXT_BASE	       0x50000000
 #define CONFIG_SYS_FLASH_BASE          0x50000000
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 #if defined(CONFIG_SCPU)
@@ -345,4 +344,9 @@ 
  */
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_INIT_SP_ADDR        \
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
 #endif  /* __CONFIG_H */