diff mbox

[U-Boot,V2,09/11] SPI: mxc_spi: add SPI clock calculation and setup to the driver

Message ID 1295513194-16158-10-git-send-email-sbabic@denx.de
State Accepted
Commit afaa9f65c24d815ed4f6133c800884921e051913
Delegated to: Stefano Babic
Headers show

Commit Message

Stefano Babic Jan. 20, 2011, 8:46 a.m. UTC 
From: Anatolij Gustschin <agust@denx.de>

The MXC SPI driver didn't calculate the SPI clock up to
now and just used highest possible divider 512 for DATA
RATE in the control register. This results in very low
transfer rates.

The patch adds code to calculate and setup the SPI clock
frequency for transfers.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Stefano Babic <sbabic@denx.de>
---
Changes:

Sergei Shtylyov:
	- fix commit message

 drivers/spi/mxc_spi.c |   23 ++++++++++++++++++++++-
 1 files changed, 22 insertions(+), 1 deletions(-)

Comments

Stefano Babic Feb. 1, 2011, 5:58 p.m. UTC | #1 
On 01/20/2011 09:46 AM, Stefano Babic wrote:
> From: Anatolij Gustschin <agust@denx.de>
> 
> The MXC SPI driver didn't calculate the SPI clock up to
> now and just used highest possible divider 512 for DATA
> RATE in the control register. This results in very low
> transfer rates.
> 
> The patch adds code to calculate and setup the SPI clock
> frequency for transfers.
> 
> Signed-off-by: Anatolij Gustschin <agust@denx.de>
> Signed-off-by: Stefano Babic <sbabic@denx.de>

Applied to u-boot-imx, thanks

Best regards,
Stefano Babic
diff mbox

Patch

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 3e99afd..ee7675b 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -199,15 +199,36 @@  void spi_cs_deactivate(struct spi_slave *slave)
 			      !(mxcs->ss_pol));
 }
 
+u32 get_cspi_div(u32 div)
+{
+	int i;
+
+	for (i = 0; i < 8; i++) {
+		if (div <= (4 << i))
+			return i;
+	}
+	return i;
+}
+
 #if defined(CONFIG_MX31) || defined(CONFIG_MX35)
 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
 		unsigned int max_hz, unsigned int mode)
 {
 	unsigned int ctrl_reg;
+	u32 clk_src;
+	u32 div;
+
+	clk_src = mxc_get_clock(MXC_CSPI_CLK);
+
+	div = clk_src / max_hz;
+	div = get_cspi_div(div);
+
+	debug("clk %d Hz, div %d, real clk %d Hz\n",
+		max_hz, div, clk_src / (4 << div));
 
 	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
 		MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
-		MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
+		MXC_CSPICTRL_DATARATE(div) |
 		MXC_CSPICTRL_EN |
 #ifdef CONFIG_MX35
 		MXC_CSPICTRL_SSCTL |