diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 96e308b..6c19d72 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -120,6 +120,9 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define MD_CNTL_WRCW		0x00080000
 #define MD_CNTL_MD_VALUE(x)	(x & 0x0000FFFF)
 
+/* DDR_CDR1 */
+#define DDR_CDR1_DHC_EN	0x80000000
+
 /* Record of register values computed */
 typedef struct fsl_ddr_cfg_regs_s {
 	struct {
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 85b6c78..6660b01 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -56,12 +56,14 @@ phys_size_t fixed_sdram(void)
 			strmhz(buf, sysinfo.freqDDRBus));
 
 	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
 	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
 
 #if (CONFIG_NUM_DDR_CONTROLLERS == 2)
 	memcpy(&ddr_cfg_regs,
 		fixed_ddr_parm_1[i].ddr_settings,
 		sizeof(ddr_cfg_regs));
+	ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
 	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
 #endif
 
@@ -143,6 +145,7 @@ typedef struct {
 	u32 datarate_mhz_high;
 	u32 n_ranks;
 	u32 clk_adjust;
+	u32 wrlvl_start;
 	u32 cpo;
 	u32 write_data_delay;
 	u32 force_2T;
@@ -162,57 +165,61 @@ typedef struct {
 /* XXX: Single rank at 800 MHz is OK.  */
 const board_specific_parameters_t board_specific_parameters[][30] = {
 	{
-	/* 	memory controller 0 			*/
-	/*	  lo|  hi|  num|  clk| cpo|wrdata|2T	*/
-	/*	 mhz| mhz|ranks|adjst|    | delay|	*/
-		{  0, 333,    4,    6,   7,    3,  0},
-		{334, 400,    4,    6,   9,    3,  0},
-		{401, 549,    4,    6,  11,    3,  0},
-		{550, 680,    4,    1,  10,    5,  0},
-		{681, 850,    4,    1,  12,    5,  0},
-		{851, 1050,   4,    1,  12,    5,  0},
-		{1051, 1250,  4,    1,  15,    4,  0},
-		{1251, 1350,  4,    1,  15,    4,  0},
-		{  0, 333,    2,    6,   7,    3,  0},
-		{334, 400,    2,    6,   9,    3,  0},
-		{401, 549,    2,    6,  11,    3,  0},
-		{550, 680,    2,    1,  10,    5,  0},
-		{681, 850,    2,    1,  12,    5,  0},
-		{851, 1050,   2,    1,  12,    5,  0},
-		{1051, 1250,  2,    1,  15,    4,  0},
-		{1251, 1350,  2,    1,  15,    4,  0},
-		{  0, 333,    1,    6,   7,    3,  0},
-		{334, 400,    1,    6,   9,    3,  0},
-		{401, 549,    1,    6,  11,    3,  0},
-		{550, 680,    1,    1,  10,    5,  0},
-		{681, 850,    1,    1,  12,    5,  0}
+	/*
+	 * memory controller 0
+	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
+	 * mhz| mhz|ranks|adjst| start | delay|
+	 */
+		{  0, 333,    4,    5,     7,   0xff,    2,  0},
+		{334, 400,    4,    5,     7,   0xff,    2,  0},
+		{401, 549,    4,    5,     7,   0xff,    2,  0},
+		{550, 680,    4,    5,     7,   0xff,    2,  0},
+		{681, 850,    4,    5,     7,   0xff,    2,  0},
+		{851, 1050,   4,    5,     7,   0xff,    2,  0},
+		{1051, 1250,  4,    5,     8,   0xff,    2,  0},
+		{1251, 1350,  4,    5,     9,   0xff,    2,  0},
+		{  0, 333,    2,    5,     7,   0xff,    2,  0},
+		{334, 400,    2,    5,     7,   0xff,    2,  0},
+		{401, 549,    2,    5,     7,   0xff,    2,  0},
+		{550, 680,    2,    5,     7,   0xff,    2,  0},
+		{681, 850,    2,    5,     7,   0xff,    2,  0},
+		{851, 1050,   2,    5,     7,   0xff,    2,  0},
+		{1051, 1250,  2,    5,     7,   0xff,    2,  0},
+		{1251, 1350,  2,    5,     7,   0xff,    2,  0},
+		{  0, 333,    1,    5,     7,   0xff,    2,  0},
+		{334, 400,    1,    5,     7,   0xff,    2,  0},
+		{401, 549,    1,    5,     7,   0xff,    2,  0},
+		{550, 680,    1,    5,     7,   0xff,    2,  0},
+		{681, 850,    1,    5,     7,   0xff,    2,  0}
 	},
 
 	{
-	/*	memory controller 1			*/
-	/*	  lo|  hi|  num|  clk| cpo|wrdata|2T	*/
-	/*	 mhz| mhz|ranks|adjst|    | delay|	*/
-		{  0, 333,    4,    6,   7,    3,  0},
-		{334, 400,    4,    6,   9,    3,  0},
-		{401, 549,    4,    6,  11,    3,  0},
-		{550, 680,    4,    1,  10,    5,  0},
-		{681, 850,    4,    1,  12,    5,  0},
-		{851, 1050,   4,    1,  12,    5,  0},
-		{1051, 1250,  4,    1,  15,    4,  0},
-		{1251, 1350,  4,    1,  15,    4,  0},
-		{  0, 333,    2,     6,  7,    3,  0},
-		{334, 400,    2,     6,  9,    3,  0},
-		{401, 549,    2,     6, 11,    3,  0},
-		{550, 680,    2,     1, 11,    6,  0},
-		{681, 850,    2,     1, 13,    6,  0},
-		{851, 1050,   2,     1, 13,    6,  0},
-		{1051, 1250,  2,     1, 15,    4,  0},
-		{1251, 1350,  2,     1, 15,    4,  0},
-		{  0, 333,    1,     6,  7,    3,  0},
-		{334, 400,    1,     6,  9,    3,  0},
-		{401, 549,    1,     6, 11,    3,  0},
-		{550, 680,    1,     1, 11,    6,  0},
-		{681, 850,    1,     1, 13,    6,  0}
+	/*
+	 * memory controller 1
+	 *  lo|  hi|  num|  clk| wrlvl | cpo  |wrdata|2T
+	 * mhz| mhz|ranks|adjst| start | delay|
+	 */
+		{  0, 333,    4,    5,     7,   0xff,    2,  0},
+		{334, 400,    4,    5,     7,   0xff,    2,  0},
+		{401, 549,    4,    5,     7,   0xff,    2,  0},
+		{550, 680,    4,    5,     7,   0xff,    2,  0},
+		{681, 850,    4,    5,     7,   0xff,    2,  0},
+		{851, 1050,   4,    5,     7,   0xff,    2,  0},
+		{1051, 1250,  4,    5,     8,   0xff,    2,  0},
+		{1251, 1350,  4,    5,     9,   0xff,    2,  0},
+		{  0, 333,    2,    5,     7,   0xff,    2,  0},
+		{334, 400,    2,    5,     7,   0xff,    2,  0},
+		{401, 549,    2,    5,     7,   0xff,    2,  0},
+		{550, 680,    2,    5,     7,   0xff,    2,  0},
+		{681, 850,    2,    5,     7,   0xff,    2,  0},
+		{851, 1050,   2,    5,     7,   0xff,    2,  0},
+		{1051, 1250,  2,    5,     7,   0xff,    2,  0},
+		{1251, 1350,  2,    5,     7,   0xff,    2,  0},
+		{  0, 333,    1,    5,     7,   0xff,    2,  0},
+		{334, 400,    1,    5,     7,   0xff,    2,  0},
+		{401, 549,    1,    5,     7,   0xff,    2,  0},
+		{550, 680,    1,    5,     7,   0xff,    2,  0},
+		{681, 850,    1,    5,     7,   0xff,    2,  0}
 	}
 };
 
@@ -227,37 +234,18 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	u32 i;
 	ulong ddr_freq;
 
-	/* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
-	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
-	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
-	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
-	 */
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i&1) {	/* odd CS */
-			popts->cs_local_opts[i].odt_rd_cfg = 0;
-			popts->cs_local_opts[i].odt_wr_cfg = 1;
-		} else {	/* even CS */
-			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
-				popts->cs_local_opts[i].odt_rd_cfg = 0;
-				popts->cs_local_opts[i].odt_wr_cfg = 1;
-			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
-			popts->cs_local_opts[i].odt_rd_cfg = 3;
-			popts->cs_local_opts[i].odt_wr_cfg = 3;
-			}
-		}
-	}
-
 	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
 	 * freqency and n_banks specified in board_specific_parameters table.
 	 */
 	ddr_freq = get_ddr_freq(0) / 1000000;
 	for (i = 0; i < num_params; i++) {
 		if (ddr_freq >= pbsp->datarate_mhz_low &&
-		    ddr_freq <= pbsp->datarate_mhz_high &&
-		    pdimm->n_ranks == pbsp->n_ranks) {
-			popts->cpo_override = 0xff; /* force auto CPO calibration */
-			popts->write_data_delay = 2;
-			popts->clk_adjust = 5; /* Force value to be 5/8 clock cycle */
+			ddr_freq <= pbsp->datarate_mhz_high &&
+			pdimm[0].n_ranks == pbsp->n_ranks) {
+			popts->cpo_override = pbsp->cpo;
+			popts->write_data_delay = pbsp->write_data_delay;
+			popts->clk_adjust = pbsp->clk_adjust;
+			popts->wrlvl_start = pbsp->wrlvl_start;
 			popts->twoT_en = pbsp->force_2T;
 		}
 		pbsp++;
@@ -272,17 +260,32 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	 * Write leveling override
 	 */
 	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xa;
-	popts->wrlvl_start = 0x7;
+	popts->wrlvl_sample = 0xf;
+
 	/*
 	 * Rtt and Rtt_WR override
 	 */
-	popts->rtt_override = 1;
-	popts->rtt_override_value = DDR3_RTT_120_OHM;
-	popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
+	popts->rtt_override = 0;
 
 	/* Enable ZQ calibration */
 	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 60 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
+
+	/* override SPD values. rcw_2 should vary at differnt speed */
+	if (pdimm[0].n_ranks == 4) {
+		popts->rcw_override = 1;
+		popts->rcw_1 = 0x000a5a00;
+		if (ddr_freq <= 800)
+			popts->rcw_2 = 0x00000000;
+		else if (ddr_freq <= 1066)
+			popts->rcw_2 = 0x00100000;
+		else if (ddr_freq <= 1333)
+			popts->rcw_2 = 0x00200000;
+		else
+			popts->rcw_2 = 0x00300000;
+	}
 }
 
 phys_size_t initdram(int board_type)
