From patchwork Tue Jul 27 13:56:10 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Graeme Smecher X-Patchwork-Id: 71797 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: wd@gemini.denx.de Delivered-To: wd@gemini.denx.de Received: from diddl.denx.de (diddl.denx.de [10.0.0.6]) by gemini.denx.de (Postfix) with ESMTP id 60BC1152398 for ; Tue, 27 Jul 2010 15:30:57 +0200 (CEST) Received: from diddl.denx.de (localhost.localdomain [127.0.0.1]) by diddl.denx.de (Postfix) with ESMTP id 49B7020F3AC6 for ; Tue, 27 Jul 2010 15:30:57 +0200 (CEST) Received: from pop.mnet-online.de by diddl.denx.de with POP3 (fetchmail-6.3.17) for (single-drop); Tue, 27 Jul 2010 15:30:57 +0200 (CEST) Received: from murder ([192.168.8.180]) by backend2 (Cyrus v2.2.12) with LMTPA; Tue, 27 Jul 2010 15:29:22 +0200 X-Sieve: CMU Sieve 2.2 Received: from mail.m-online.net (localhost [127.0.0.1]) by frontend1.mail.m-online.net (Cyrus v2.2.12) with LMTPA; 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Tue, 27 Jul 2010 15:28:52 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 060E528119 for ; Tue, 27 Jul 2010 15:28:50 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GeA+0CwvzzZw for ; Tue, 27 Jul 2010 15:28:49 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from trickle.cc.mcgill.ca (trickle.CC.McGill.CA [132.206.27.51]) by theia.denx.de (Postfix) with ESMTP id BB47A2811A for ; Tue, 27 Jul 2010 15:28:43 +0200 (CEST) Received: from drizzle.cc.mcgill.ca (drizzle.CC.McGill.CA [132.206.27.48]) by trickle.cc.mcgill.ca (8.13.6/8.12.3) with ESMTP id o6RDNAAP002635 for ; Tue, 27 Jul 2010 09:23:10 -0400 (EDT) Received: from mailscan2.ncs.mcgill.ca (mailscan2.NCS.McGill.CA [132.216.77.249]) by drizzle.cc.mcgill.ca (8.12.11.20060308/8.12.3) with ESMTP id o6RDN7jb026490 for ; Tue, 27 Jul 2010 09:23:07 -0400 Received: from mailscan2.ncs.mcgill.ca (localhost [127.0.0.1]) by localhost (Postfix) with SMTP id 4953A2F9C; Tue, 27 Jul 2010 09:23:07 -0400 (EDT) Received: from localhost.localdomain (northpost.physics.mcgill.ca [132.206.126.243]) by mailscan2.ncs.mcgill.ca (Postfix) with ESMTP id 20688319A; Tue, 27 Jul 2010 09:23:07 -0400 (EDT) From: Graeme Smecher To: u-boot@lists.denx.de Date: Tue, 27 Jul 2010 09:56:10 -0400 Message-Id: <1280238970-21591-2-git-send-email-graeme.smecher@mail.mcgill.ca> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1280238970-21591-1-git-send-email-graeme.smecher@mail.mcgill.ca> References: <1280238970-21591-1-git-send-email-graeme.smecher@mail.mcgill.ca> X-PMX-Version: 5.4.2.338381, Antispam-Engine: 2.6.0.325393, Antispam-Data: 2010.6.9.160619 X-McGill-WhereFrom: Internal Subject: [U-Boot] [PATCH] Adds driver for Xilinx' xps_spi SPI controller X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Virus-Scanned: by amavisd-new at m-online.net --- drivers/spi/Makefile | 1 + drivers/spi/xilinx_spi.c | 171 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 172 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/xilinx_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index dfcbb8b..34e0f31 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libspi.a COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o +COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c new file mode 100644 index 0000000..99ce661 --- /dev/null +++ b/drivers/spi/xilinx_spi.c @@ -0,0 +1,171 @@ +/* + * Xilinx SPI driver + * + * based on bfin_spi.c, by way of altera_spi.c + * Copyright (c) 2005-2008 Analog Devices Inc. + * Copyright (c) 2010 Thomas Chou + * Copyright (c) 2010 Graeme Smecher + * + * Licensed under the GPL-2 or later. + */ +#include +#include +#include +#include + +#define debug printf + +#define XILINX_SPI_RR 0x6c +#define XILINX_SPI_TR 0x68 +#define XILINX_SPI_SR 0x64 +#define XILINX_SPI_CR 0x60 +#define XILINX_SPI_SSR 0x70 + +#define XILINX_SPI_SR_RX_EMPTY_MSK 0x01 + +#define XILINX_SPI_CR_DEFAULT (0x0086) + +#if XPAR_XSPI_NUM_INSTANCES > 4 +# warning "The xilinx_spi driver will ignore some of your SPI peripherals!" +#endif + +static ulong xilinx_spi_base_list[] = { +#ifdef XPAR_SPI_0_BASEADDR + XPAR_SPI_0_BASEADDR, +#endif +#ifdef XPAR_SPI_1_BASEADDR + XPAR_SPI_1_BASEADDR, +#endif +#ifdef XPAR_SPI_2_BASEADDR + XPAR_SPI_2_BASEADDR, +#endif +#ifdef XPAR_SPI_3_BASEADDR + XPAR_SPI_3_BASEADDR, +#endif +}; + +struct xilinx_spi_slave { + struct spi_slave slave; + ulong base; +}; +#define to_xilinx_spi_slave(s) container_of(s, struct xilinx_spi_slave, slave) + +__attribute__((weak)) +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32; +} + +__attribute__((weak)) +void spi_cs_activate(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + writel(~(1 << slave->cs), xilspi->base + XILINX_SPI_SSR); +} + +__attribute__((weak)) +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + writel(~0, xilspi->base + XILINX_SPI_SSR); +} + +void spi_init(void) +{ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct xilinx_spi_slave *xilspi; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + xilspi = malloc(sizeof(*xilspi)); + if (!xilspi) + return NULL; + + xilspi->slave.bus = bus; + xilspi->slave.cs = cs; + xilspi->base = xilinx_spi_base_list[bus]; + debug("%s: bus:%i cs:%i base:%lx\n", __func__, + bus, cs, xilspi->base); + + writel(XILINX_SPI_CR_DEFAULT, xilspi->base + XILINX_SPI_CR); + + return &xilspi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + free(xilspi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + writel(~0, xilspi->base + XILINX_SPI_SSR); + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); + writel(~0, xilspi->base + XILINX_SPI_SSR); +} + +#ifndef CONFIG_XILINX_SPI_IDLE_VAL +# define CONFIG_XILINX_SPI_IDLE_VAL 0xff +#endif + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave); + /* assume spi core configured to do 8 bit transfers */ + uint bytes = bitlen / 8; + const uchar *txp = dout; + uchar *rxp = din; + + debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, + slave->bus, slave->cs, bitlen, bytes, flags); + if (bitlen == 0) + goto done; + + if (bitlen % 8) { + flags |= SPI_XFER_END; + goto done; + } + + /* empty read buffer */ + while (!(readl(xilspi->base + XILINX_SPI_SR) & + XILINX_SPI_SR_RX_EMPTY_MSK)) + readl(xilspi->base + XILINX_SPI_RR); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (bytes--) { + uchar d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; + debug("%s: tx:%x ", __func__, d); + writel(d, xilspi->base + XILINX_SPI_TR); + while (readl(xilspi->base + XILINX_SPI_SR) & + XILINX_SPI_SR_RX_EMPTY_MSK) + ; + d = readl(xilspi->base + XILINX_SPI_RR); + if (rxp) + *rxp++ = d; + debug("rx:%x\n", d); + } + done: + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +}