From patchwork Tue Aug 14 15:19:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= X-Patchwork-Id: 177342 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C2A702C0083 for ; Wed, 15 Aug 2012 01:14:29 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 20FD6280C1; Tue, 14 Aug 2012 17:14:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VvvLgywIQ9mn; Tue, 14 Aug 2012 17:14:27 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5E00128148; Tue, 14 Aug 2012 17:14:26 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 27F0628148 for ; Tue, 14 Aug 2012 17:14:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id f8i3Js2+hxX5 for ; Tue, 14 Aug 2012 17:14:24 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from zose-mta11.web4all.fr (zose-mta11.web4all.fr [178.33.204.87]) by theia.denx.de (Postfix) with ESMTP id BAB52280C1 for ; Tue, 14 Aug 2012 17:14:23 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zose-mta11.web4all.fr (Postfix) with ESMTP id B15A246015; Tue, 14 Aug 2012 17:19:09 +0200 (CEST) X-Virus-Scanned: amavisd-new at zose1.web4all.fr Received: from zose-mta11.web4all.fr ([127.0.0.1]) by localhost (zose-mta11.web4all.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Vj-Mlb6Hodio; Tue, 14 Aug 2012 17:19:09 +0200 (CEST) Received: from zose-store12.web4all.fr (zose-store12.web4all.fr [178.33.204.49]) by zose-mta11.web4all.fr (Postfix) with ESMTP id 4256146016; Tue, 14 Aug 2012 17:19:09 +0200 (CEST) Date: Tue, 14 Aug 2012 17:19:43 +0200 (CEST) From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= To: U-Boot-Users ML Message-ID: <1179733873.2404125.1344957583298.JavaMail.root@advansee.com> In-Reply-To: MIME-Version: 1.0 X-Originating-IP: [88.188.188.98] X-Mailer: Zimbra 7.2.0_GA_2669 (ZimbraWebClient - FF3.0 (Win)/7.2.0_GA_2669) Subject: [U-Boot] [PATCH v2 3/4] mx5: Optimize lowlevel_init for TO 3 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The mx5 lowlevel_init.S contains code that detects the silicon revision at runtime, and that behaves differently if a silicon revision older than TO 3 is detected. This code is useless for recently designed boards that may not be fitted with older silicon revisions. Hence, this patch adds an option to optimize away this revision-specific code from lowlevel_init.S. Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic --- Changes for v2: - Make patch description more detailed. .../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 4 ++-- .../doc/README.imx5 | 7 ++++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 529e35b..d0f75fa 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -42,7 +42,7 @@ 1 << 23 | /* disable write allocate combine */ \ 1 << 22 /* disable write allocate */ -#if defined(CONFIG_MX51) +#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3) ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 @@ -244,7 +244,7 @@ setup_pll_func: ldr r0, =CCM_BASE_ADDR -#if defined(CONFIG_MX51) +#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3) /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 diff --git u-boot-4d3c95f.orig/doc/README.imx5 u-boot-4d3c95f/doc/README.imx5 index f7eab7d..938d3da 100644 --- u-boot-4d3c95f.orig/doc/README.imx5 +++ u-boot-4d3c95f/doc/README.imx5 @@ -6,7 +6,12 @@ i.MX5x SoCs. 1. CONFIGURATION OPTIONS/SETTINGS --------------------------------- -1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata. +1.1 CONFIG_MX51_TO_3: i.MX51 silicon revision 3 or higher. + This option can be enabled for these i.MX51 silicon revisions to optimize + away some specific behavior triggered by the detection of older silicon + revisions at runtime. + +1.2 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata. This option should be enabled by all boards using the i.MX51 silicon version up until (including) 3.0 running at 800MHz. The PLL's in the i.MX51 processor can go out of lock due to a metastable