| Message ID | 1179733873.2404125.1344957583298.JavaMail.root@advansee.com |
|---|---|
| State | Rejected |
| Delegated to: | Stefano Babic |
| Headers | show |
On 14/08/2012 17:19, Benoît Thébaudeau wrote: > The mx5 lowlevel_init.S contains code that detects the silicon revision at > runtime, and that behaves differently if a silicon revision older than TO 3 is > detected. This code is useless for recently designed boards that may not be > fitted with older silicon revisions. Hence, this patch adds an option to > optimize away this revision-specific code from lowlevel_init.S. > > Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> > Cc: Stefano Babic <sbabic@denx.de> > --- Hi Benoît, > Changes for v2: > - Make patch description more detailed. > > .../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 4 ++-- > .../doc/README.imx5 | 7 ++++++- > 2 files changed, 8 insertions(+), 3 deletions(-) > The ROM revision is currently detected at run time - because this does not fix an evident bug, your patch intends to reduce the footprint. Then I chacked on a mx51evk, a board thet was shipped by Freescale with TO 2 (and maybe TO 1 ?), and there are surely samples with TO2 or TO3 in the world. Without the poatch: Configuring for mx51evk - Board: mx51evk, Options: IMX_CONFIG=board/freescale/mx51evk/imximage.cfg text data bss dec hex filename 258168 15872 268464 542504 84728 ./u-boot With the patch: Configuring for mx51evk - Board: mx51evk, Options: IMX_CONFIG=board/freescale/mx51evk/imximage.cfg text data bss dec hex filename 258140 15872 268492 542504 84728 ./u-boot We win only 28 bytes - on the other side, we had a CONFIG_ that is not so clear how to be used, mainly if a board as the mx51evk was shipped with both versions. I think the advantages are negligible here. Best regards, Stefano
Hi Stefano, > On 14/08/2012 17:19, Benoît Thébaudeau wrote: > > The mx5 lowlevel_init.S contains code that detects the silicon > > revision at > > runtime, and that behaves differently if a silicon revision older > > than TO 3 is > > detected. This code is useless for recently designed boards that > > may not be > > fitted with older silicon revisions. Hence, this patch adds an > > option to > > optimize away this revision-specific code from lowlevel_init.S. > > > > Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> > > Cc: Stefano Babic <sbabic@denx.de> > > --- > > Hi Benoît, > > > Changes for v2: > > - Make patch description more detailed. > > > > .../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 4 ++-- > > .../doc/README.imx5 | 7 ++++++- > > 2 files changed, 8 insertions(+), 3 deletions(-) > > > > The ROM revision is currently detected at run time - because this > does > not fix an evident bug, your patch intends to reduce the footprint. > > Then I chacked on a mx51evk, a board thet was shipped by Freescale > with > TO 2 (and maybe TO 1 ?), and there are surely samples with TO2 or TO3 > in > the world. > > Without the poatch: > > Configuring for mx51evk - Board: mx51evk, Options: > IMX_CONFIG=board/freescale/mx51evk/imximage.cfg > text data bss dec hex filename > 258168 15872 268464 542504 84728 ./u-boot > > With the patch: > > Configuring for mx51evk - Board: mx51evk, Options: > IMX_CONFIG=board/freescale/mx51evk/imximage.cfg > text data bss dec hex filename > 258140 15872 268492 542504 84728 ./u-boot > > We win only 28 bytes - on the other side, we had a CONFIG_ that is > not > so clear how to be used, mainly if a board as the mx51evk was shipped > with both versions. To make things easier, this config should be used only for boards always shipped with the newer versions. > I think the advantages are negligible here. Indeed. I needed that for a specific case where any single byte was worth saving. For upstream U-Boot, I let you decide if this is interesting enough or not. Best regards, Benoît
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 529e35b..d0f75fa 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -42,7 +42,7 @@ 1 << 23 | /* disable write allocate combine */ \ 1 << 22 /* disable write allocate */ -#if defined(CONFIG_MX51) +#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3) ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 @@ -244,7 +244,7 @@ setup_pll_func: ldr r0, =CCM_BASE_ADDR -#if defined(CONFIG_MX51) +#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3) /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 diff --git u-boot-4d3c95f.orig/doc/README.imx5 u-boot-4d3c95f/doc/README.imx5 index f7eab7d..938d3da 100644 --- u-boot-4d3c95f.orig/doc/README.imx5 +++ u-boot-4d3c95f/doc/README.imx5 @@ -6,7 +6,12 @@ i.MX5x SoCs. 1. CONFIGURATION OPTIONS/SETTINGS --------------------------------- -1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata. +1.1 CONFIG_MX51_TO_3: i.MX51 silicon revision 3 or higher. + This option can be enabled for these i.MX51 silicon revisions to optimize + away some specific behavior triggered by the detection of older silicon + revisions at runtime. + +1.2 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata. This option should be enabled by all boards using the i.MX51 silicon version up until (including) 3.0 running at 800MHz. The PLL's in the i.MX51 processor can go out of lock due to a metastable
The mx5 lowlevel_init.S contains code that detects the silicon revision at runtime, and that behaves differently if a silicon revision older than TO 3 is detected. This code is useless for recently designed boards that may not be fitted with older silicon revisions. Hence, this patch adds an option to optimize away this revision-specific code from lowlevel_init.S. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> --- Changes for v2: - Make patch description more detailed. .../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 4 ++-- .../doc/README.imx5 | 7 ++++++- 2 files changed, 8 insertions(+), 3 deletions(-)