diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx31/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx31/imx-regs.h
index 7ddbbd6..6ec5fa7 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -567,7 +567,8 @@ struct esdc_regs {
 
 #define MX31_IIM_BASE_ADDR	0x5001C000
 
-#define PDR0_CSI_PODF(x)	(((x) & 0x1ff) << 23)
+#define PDR0_CSI_PODF(x)	(((x) & 0x3f) << 26)
+#define PDR0_CSI_PRDF(x)	(((x) & 0x7) << 23)
 #define PDR0_PER_PODF(x)	(((x) & 0x1f) << 16)
 #define PDR0_HSP_PODF(x)	(((x) & 0x7) << 11)
 #define PDR0_NFC_PODF(x)	(((x) & 0x7) << 8)
@@ -580,7 +581,8 @@ struct esdc_regs {
 #define PLL_MFI(x)		(((x) & 0xf) << 10)
 #define PLL_MFN(x)		(((x) & 0x3ff) << 0)
 
-#define GET_PDR0_CSI_PODF(x)	(((x) >> 23) & 0x1ff)
+#define GET_PDR0_CSI_PODF(x)	(((x) >> 26) & 0x3f)
+#define GET_PDR0_CSI_PRDF(x)	(((x) >> 23) & 0x7)
 #define GET_PDR0_PER_PODF(x)	(((x) >> 16) & 0x1f)
 #define GET_PDR0_HSP_PODF(x)	(((x) >> 11) & 0x7)
 #define GET_PDR0_NFC_PODF(x)	(((x) >> 8) & 0x7)
diff --git u-boot-4d3c95f.orig/board/freescale/mx31ads/lowlevel_init.S u-boot-4d3c95f/board/freescale/mx31ads/lowlevel_init.S
index 5c18bc1..2972065 100644
--- u-boot-4d3c95f.orig/board/freescale/mx31ads/lowlevel_init.S
+++ u-boot-4d3c95f/board/freescale/mx31ads/lowlevel_init.S
@@ -246,8 +246,8 @@ lowlevel_init:
 	/* COSR */
 	str	r1, [r0, #0x1c]
 
-	/* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
-/*	REG	CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
+	/* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
+/*	REG	CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
 
 	/* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
 /*	REG	CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
diff --git u-boot-4d3c95f.orig/board/hale/tt01/tt01.c u-boot-4d3c95f/board/hale/tt01/tt01.c
index 02e75ed..143fcef 100644
--- u-boot-4d3c95f.orig/board/hale/tt01/tt01.c
+++ u-boot-4d3c95f/board/hale/tt01/tt01.c
@@ -52,7 +52,7 @@ static void board_setup_clocks(void)
 	writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
 
 	/* Set up clock to 532MHz */
-	writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |
+	writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
 			PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
 			PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
 			PDR0_MCU_PODF(0), &ccm->pdr0);
diff --git u-boot-4d3c95f.orig/board/imx31_phycore/lowlevel_init.S u-boot-4d3c95f/board/imx31_phycore/lowlevel_init.S
index c47137d..4dd78b6 100644
--- u-boot-4d3c95f.orig/board/imx31_phycore/lowlevel_init.S
+++ u-boot-4d3c95f/board/imx31_phycore/lowlevel_init.S
@@ -54,7 +54,7 @@ lowlevel_init:
 	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE
 	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
 
-	REG	CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |	PDR0_MCU_PODF(0)
+	REG	CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
 
 	REG	CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
 
diff --git u-boot-4d3c95f.orig/board/logicpd/imx31_litekit/lowlevel_init.S u-boot-4d3c95f/board/logicpd/imx31_litekit/lowlevel_init.S
index 95b0c08..0ce8905 100644
--- u-boot-4d3c95f.orig/board/logicpd/imx31_litekit/lowlevel_init.S
+++ u-boot-4d3c95f/board/logicpd/imx31_litekit/lowlevel_init.S
@@ -54,7 +54,7 @@ lowlevel_init:
 	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE
 	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
 
-	REG	CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
+	REG	CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
 
 	REG	CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
 	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
diff --git u-boot-4d3c95f.orig/include/configs/mx31pdk.h u-boot-4d3c95f/include/configs/mx31pdk.h
index 7634de7..4900be0 100644
--- u-boot-4d3c95f.orig/include/configs/mx31pdk.h
+++ u-boot-4d3c95f/include/configs/mx31pdk.h
@@ -212,11 +212,11 @@
 
 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
 #define CCM_CCMR_SETUP		0x074B0BF5
-#define CCM_PDR0_SETUP_532MHZ	(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
-				 PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |     \
-				 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |     \
-				 PDR0_MCU_PODF(0))
-#define CCM_MPCTL_SETUP_532MHZ	(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |   \
+#define CCM_PDR0_SETUP_532MHZ	(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
+				 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) |    \
+				 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |    \
+				 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
+#define CCM_MPCTL_SETUP_532MHZ	(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
 				 PLL_MFN(12))
 
 #define ESDMISC_MDDR_SETUP	0x00000004
