From patchwork Tue Aug 14 18:07:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= X-Patchwork-Id: 177408 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4D1442C0089 for ; Wed, 15 Aug 2012 04:02:38 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DEDEF28162; Tue, 14 Aug 2012 20:02:36 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nOiOwTW97hvd; Tue, 14 Aug 2012 20:02:36 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 276B028140; Tue, 14 Aug 2012 20:02:33 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A60B228151 for ; Tue, 14 Aug 2012 20:02:30 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qPPiHr6fQWFr for ; Tue, 14 Aug 2012 20:02:30 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from zose-mta11.web4all.fr (zose-mta-11.w4a.fr [178.33.204.86]) by theia.denx.de (Postfix) with ESMTP id 21FDC28140 for ; Tue, 14 Aug 2012 20:02:22 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by zose-mta11.web4all.fr (Postfix) with ESMTP id 521544601D; Tue, 14 Aug 2012 20:07:09 +0200 (CEST) X-Virus-Scanned: amavisd-new at zose1.web4all.fr Received: from zose-mta11.web4all.fr ([127.0.0.1]) by localhost (zose-mta11.web4all.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FrG6Z+HVigph; Tue, 14 Aug 2012 20:07:09 +0200 (CEST) Received: from zose-store12.web4all.fr (zose-store12.web4all.fr [178.33.204.49]) by zose-mta11.web4all.fr (Postfix) with ESMTP id 14DC346015; Tue, 14 Aug 2012 20:07:09 +0200 (CEST) Date: Tue, 14 Aug 2012 20:07:43 +0200 (CEST) From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= To: U-Boot-Users ML Message-ID: <100121725.2408596.1344967663150.JavaMail.root@advansee.com> In-Reply-To: <1102157688.2408541.1344967559029.JavaMail.root@advansee.com> MIME-Version: 1.0 X-Originating-IP: [88.188.188.98] X-Mailer: Zimbra 7.2.0_GA_2669 (ZimbraWebClient - FF3.0 (Win)/7.2.0_GA_2669) Cc: Marek Vasut Subject: [U-Boot] [PATCH 07/10] mx5 clocks: Fix get_uart_clk() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic --- .../arch/arm/cpu/armv7/mx5/clock.c | 45 ++++++++++++-------- 1 file changed, 27 insertions(+), 18 deletions(-) diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c index b13c55a..75a6eae 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/clock.c +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c @@ -378,31 +378,40 @@ static u32 get_ipg_per_clk(void) return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); } +/* Get the output clock rate of a standard PLL MUX for peripherals. */ +static u32 get_standard_pll_sel_clk(u32 clk_sel) +{ + u32 freq; + + switch (clk_sel & 0x3) { + case 0: + freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); + break; + case 1: + freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK); + break; + case 2: + freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK); + break; + case 3: + freq = get_lp_apm(); + break; + } + + return freq; +} + /* * Get the rate of uart clk. */ static u32 get_uart_clk(void) { - unsigned int freq, reg, pred, podf; + unsigned int clk_sel, freq, reg, pred, podf; reg = __raw_readl(&mxc_ccm->cscmr1); - switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >> - MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) { - case 0x0: - freq = decode_pll(mxc_plls[PLL1_CLOCK], - CONFIG_SYS_MX5_HCLK); - break; - case 0x1: - freq = decode_pll(mxc_plls[PLL2_CLOCK], - CONFIG_SYS_MX5_HCLK); - break; - case 0x2: - freq = decode_pll(mxc_plls[PLL3_CLOCK], - CONFIG_SYS_MX5_HCLK); - break; - default: - return 66500000; - } + clk_sel = (reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >> + MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; + freq = get_standard_pll_sel_clk(clk_sel); reg = __raw_readl(&mxc_ccm->cscdr1);