From patchwork Mon Jan 20 12:20:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 1225904 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=tkos.co.il Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 481W3D1MDqz9sP6 for ; Mon, 20 Jan 2020 23:20:39 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2C09F81995; Mon, 20 Jan 2020 13:20:33 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tkos.co.il Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id D37E48189E; Mon, 20 Jan 2020 13:20:30 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=KHOP_HELO_FCRDNS, SPF_HELO_NONE, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from mx.tkos.co.il (guitar.tcltek.co.il [192.115.133.116]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4AEEF817C3 for ; Mon, 20 Jan 2020 13:20:26 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=tkos.co.il Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=baruch@tkos.co.il Received: from tarshish.tkos.co.il (unknown [10.0.8.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id 29D554407C1; Mon, 20 Jan 2020 14:20:25 +0200 (IST) From: Baruch Siach To: u-boot@lists.denx.de, Stefan Roese Subject: [PATCH v2 01/10] ddr: marvell: a38x: allow board specific clock out setup Date: Mon, 20 Jan 2020 14:20:06 +0200 Message-Id: <0b7a38d599638c64e11d44151c8965b56db32ea8.1579522639.git.baruch@tkos.co.il> X-Mailer: git-send-email 2.24.1 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.26 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Baruch Siach , Dennis Gilmore , Chris Packham Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.101.4 at phobos.denx.de X-Virus-Status: Clean DDR clock out might be unrelated to the number of active chip-select. For example, the board might have two DDR components, but only one chip-select. The clk_enable mask allows the board to enable DDR clocks regardless of active chip-selects. Reviewed-by: Stefan Roese Signed-off-by: Baruch Siach --- drivers/ddr/marvell/a38x/ddr3_training.c | 10 ++++++++-- drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 +++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index c7be700d641f..9718f18c3024 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -280,8 +280,14 @@ int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) { u32 data, addr_hi, data_high; u32 mem_index; + u32 clk_enable; struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + if (tm->clk_enable & (1 << cs_num)) + clk_enable = 1; + else + clk_enable = enable; + if (enable == 1) { data = (tm->interface_params[if_id].bus_width == MV_DDR_DEV_WIDTH_8BIT) ? 0 : 1; @@ -316,13 +322,13 @@ int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) case 2: CHECK_STATUS(ddr3_tip_if_write (dev_num, ACCESS_TYPE_UNICAST, if_id, - DUNIT_CTRL_LOW_REG, (enable << (cs_num + 11)), + DUNIT_CTRL_LOW_REG, (clk_enable << (cs_num + 11)), 1 << (cs_num + 11))); break; case 3: CHECK_STATUS(ddr3_tip_if_write (dev_num, ACCESS_TYPE_UNICAST, if_id, - DUNIT_CTRL_LOW_REG, (enable << 15), 1 << 15)); + DUNIT_CTRL_LOW_REG, (clk_enable << 15), 1 << 15)); break; } diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index e6fe8a04289b..950f296ff984 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -124,6 +124,9 @@ struct mv_ddr_topology_map { /* electrical parameters */ unsigned int electrical_data[MV_DDR_EDATA_LAST]; + + /* Clock enable mask */ + u32 clk_enable; }; enum mv_ddr_iface_mode {