From patchwork Thu Aug 19 11:42:33 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Jander X-Patchwork-Id: 71823 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: wd@gemini.denx.de Delivered-To: wd@gemini.denx.de Received: from diddl.denx.de (diddl.denx.de [10.0.0.6]) by gemini.denx.de (Postfix) with ESMTP id 9AB4B157D71 for ; Thu, 19 Aug 2010 14:11:34 +0200 (CEST) Received: from diddl.denx.de (localhost.localdomain [127.0.0.1]) by diddl.denx.de (Postfix) with ESMTP id 7F29C316EC0F for ; Thu, 19 Aug 2010 14:11:34 +0200 (MEST) Received: from pop.mnet-online.de by diddl.denx.de with POP3 (fetchmail-6.3.17) for (single-drop); Thu, 19 Aug 2010 14:11:34 +0200 (MEST) Received: from murder ([192.168.8.180]) by backend2 (Cyrus v2.2.12) with LMTPA; Thu, 19 Aug 2010 14:11:14 +0200 X-Sieve: CMU Sieve 2.2 Received: from mail.m-online.net (localhost [127.0.0.1]) by frontend1.mail.m-online.net (Cyrus v2.2.12) with LMTPA; Thu, 19 Aug 2010 14:11:14 +0200 Received: from scanner-1.m-online.net (scanner-1.mail.m-online.net [192.168.8.165]) by mail.m-online.net (Postfix) with ESMTP id 772131C00284; Thu, 19 Aug 2010 14:11:14 +0200 (CEST) Received: from mxin-3.m-online.net ([192.168.6.165]) by scanner-1.m-online.net (scanner-1.m-online.net [192.168.8.165]) (amavisd-new, port 10026) with ESMTP id 14901-01-4; Thu, 19 Aug 2010 14:11:11 +0200 (CEST) Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by mxin-3.m-online.net (Postfix) with ESMTP id 79F9546F3F4; Thu, 19 Aug 2010 14:11:10 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 585FC28098; Thu, 19 Aug 2010 14:10:17 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id D0pcSCppepB4; Thu, 19 Aug 2010 14:10:17 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CD402280B2; Thu, 19 Aug 2010 14:09:53 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 75CE928085 for ; Thu, 19 Aug 2010 14:09:48 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lXi4wP7t8dnR for ; Thu, 19 Aug 2010 14:09:42 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from protonic.prtnl (protonic.xs4all.nl [213.84.116.84]) by theia.denx.de (Postfix) with ESMTP id 0A8E028086 for ; Thu, 19 Aug 2010 14:09:38 +0200 (CEST) Received: from localhost.localdomain (archvile.prtnl [192.168.1.153]) by protonic.prtnl (Postfix) with ESMTP id F20AA29EBD; Thu, 19 Aug 2010 13:43:06 +0200 (CEST) From: David Jander To: u-boot@lists.denx.de Date: Thu, 19 Aug 2010 13:42:33 +0200 Message-Id: <00b6eb8822a36b67a5e6154fd256e51e605fe47a.1282213859.git.david@protonic.nl> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <3b6cafa5af1ffc86641912d81a423ec0d2f39ba6.1282213859.git.david@protonic.nl> References: <1282218154-5564-1-git-send-email-david@protonic.nl> <2742a1d58389e0f76fee54c9833ac4d98039a5c4.1282213859.git.david@protonic.nl> <3b6cafa5af1ffc86641912d81a423ec0d2f39ba6.1282213859.git.david@protonic.nl> In-Reply-To: <2742a1d58389e0f76fee54c9833ac4d98039a5c4.1282213859.git.david@protonic.nl> References: <2742a1d58389e0f76fee54c9833ac4d98039a5c4.1282213859.git.david@protonic.nl> Cc: David Jander Subject: [U-Boot] [PATCH 4/4] Added initial support for PRTLVT2-based boards. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Virus-Scanned: by amavisd-new at m-online.net Signed-off-by: David Jander --- board/Protonic/prtlvt2/Makefile | 48 ++++ board/Protonic/prtlvt2/config.mk | 25 ++ board/Protonic/prtlvt2/imximage.cfg | 171 ++++++++++++ board/Protonic/prtlvt2/prtlvt2.c | 513 +++++++++++++++++++++++++++++++++++ board/Protonic/prtlvt2/prtlvt2.h | 50 ++++ boards.cfg | 1 + include/configs/prtlvt2.h | 203 ++++++++++++++ 7 files changed, 1011 insertions(+), 0 deletions(-) create mode 100644 board/Protonic/prtlvt2/Makefile create mode 100644 board/Protonic/prtlvt2/config.mk create mode 100644 board/Protonic/prtlvt2/imximage.cfg create mode 100644 board/Protonic/prtlvt2/prtlvt2.c create mode 100644 board/Protonic/prtlvt2/prtlvt2.h create mode 100644 include/configs/prtlvt2.h diff --git a/board/Protonic/prtlvt2/Makefile b/board/Protonic/prtlvt2/Makefile new file mode 100644 index 0000000..e1f1157 --- /dev/null +++ b/board/Protonic/prtlvt2/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := prtlvt2.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/Protonic/prtlvt2/config.mk b/board/Protonic/prtlvt2/config.mk new file mode 100644 index 0000000..af70ec2 --- /dev/null +++ b/board/Protonic/prtlvt2/config.mk @@ -0,0 +1,25 @@ +# +# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds +TEXT_BASE = 0x97800000 +IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg diff --git a/board/Protonic/prtlvt2/imximage.cfg b/board/Protonic/prtlvt2/imximage.cfg new file mode 100644 index 0000000..a89168e --- /dev/null +++ b/board/Protonic/prtlvt2/imximage.cfg @@ -0,0 +1,171 @@ +# +# (C Copyright 2009 +# Stefano Babic DENX Software Engineering sbabic@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# Boot Device : one of +# spi, sd (the board has no nand neither onenand) + +# BOOT_FROM spi +BOOT_FROM sd + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register + +# Setting IOMUXC + +# DS = Drive Strength +# SR = Slew Rate + +# DDR Input mode: DDR +DATA 4 0x73FA88a0 0x200 + +# SDODT0/1: 100k Pull-Down, DS-high, SR-fast +DATA 4 0x73FA8510 0x20c5 +DATA 4 0x73FA850c 0x20c5 + +# DDR A0...A7: DS-medium +DATA 4 0x73FA883c 0x2 + +# DDR A8...A14, SDBA0...SDBA2: DS-medium +DATA 4 0x73FA8848 0x2 + +# DDR SDCLK: 100k Pull-Up, DS-max, SR-fast +DATA 4 0x73FA84b8 0xe7 + +# DDR DQS0...DQS3: No pull/keeper, DS-high, SR-fast +DATA 4 0x73FA84bc 0x45 +DATA 4 0x73FA84c0 0x45 +DATA 4 0x73FA84c4 0x45 +DATA 4 0x73FA84c8 0x45 + +# DDR: Disable pull/keeper on all data lines +DATA 4 0x73FA8820 0x0 + +# DDR RAS, CAS: DS-medium, SR-fast +DATA 4 0x73FA84a4 0x3 +DATA 4 0x73FA84a8 0x3 + +# DDR WE, SDCKE0, SDCKE1: 100k Pull-Up, DS-medium, SR-fast +DATA 4 0x73FA84ac 0xe3 +DATA 4 0x73FA84b0 0xe3 +DATA 4 0x73FA84b4 0xe3 + +# DDR CS0, CS1: 100k Pull-Up, DS-medium, SR-fast +DATA 4 0x73FA84cc 0xe3 +DATA 4 0x73FA84d0 0xe2 + +# DDR Data D24...D31, D0...D23: DS-high +DATA 4 0x73FA882c 0x5 +DATA 4 0x73FA88a4 0x5 +DATA 4 0x73FA88ac 0x5 +DATA 4 0x73FA88b8 0x5 + +# Setting DDR for micron +# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model +# CAS=3 BL=4 +# ESDCTL_ESDCTL0: Enable, No refresh, 13-bit ROW, +# DBL_tRFC, 10-bit COL, 32-bit data, Run mode. +# ESDCTL_ESDCTL1: idem. +DATA 4 0x83FD9000 0x82a20000 +DATA 4 0x83FD9008 0x82a20000 + +# ESDCTL_ESDMISC: ODT off, A10 is precharge, +# Diff_DQS, AUTO_DLL_PAUSE, Bank-interleave, RALAT=1, +# 8-bank, DDR2_EN +DATA 4 0x83FD9010 0x000ad0d0 + +# ESDCTL_ESDCFG0: tRFC=13ck, tXSR=28ck, tXP=2ck, +# tWTR=2ck, tRP=3ck, tMRD=2ck, tRAS=8ck, tRRD=2ck, +# tWR=3ck, tRCD=3ck, tRC=11ck +# ESDCTL_ESDCFG1: idem. +DATA 4 0x83FD9004 0x333574aa +DATA 4 0x83FD900C 0x333574aa + +# Init DRAM on CS0 +# ESDCTL_ESDSCR +# 1. Precharge ALL +DATA 4 0x83FD9014 0x04008008 +# 2. LMR EMR2: 1x Refresh (0...85C) +DATA 4 0x83FD9014 0x0000801a +# 3. LMR EMR3: Clear EMR3 (not used) +DATA 4 0x83FD9014 0x0000801b +# 4. LMR EMR: Rtt = 50 Ohm, Diff-DQS +DATA 4 0x83FD9014 0x00448019 +# 5. LMR MR: BL=4, Seq, CL3, WR4, DLL-reset +DATA 4 0x83FD9014 0x07328018 +# 6. Precharge ALL +DATA 4 0x83FD9014 0x04008008 +# 7. Auto Refresh +DATA 4 0x83FD9014 0x00008010 +# 8. Auto Refresh +DATA 4 0x83FD9014 0x00008010 +# 9. LMR MR: BL=4, Seq, CL3, WR4 +DATA 4 0x83FD9014 0x06328018 +# 10. LMR EMR: Load OCD defaults +DATA 4 0x83FD9014 0x03808019 +# 11. LMR EMR: Rtt = 150 Ohm, Diff-DQS, Reduced DS +DATA 4 0x83FD9014 0x00428019 +# 12. NOP +DATA 4 0x83FD9014 0x00008000 + +# Init DRAM on CS1 +# Same sequence as for CS0, only CS=1. +DATA 4 0x83FD9014 0x0400800c +DATA 4 0x83FD9014 0x0000801e +DATA 4 0x83FD9014 0x0000801f +DATA 4 0x83FD9014 0x0000801d +DATA 4 0x83FD9014 0x0732801c +DATA 4 0x83FD9014 0x0400800c +DATA 4 0x83FD9014 0x00008014 +DATA 4 0x83FD9014 0x00008014 +DATA 4 0x83FD9014 0x0632801c +DATA 4 0x83FD9014 0x0380801d +DATA 4 0x83FD9014 0x0042801d +DATA 4 0x83FD9014 0x00008004 + +# ESDCTL_ESDCTL0: Enable, SREFR=7.81us, 13-bit ROW, +# DBL_tRFC, 10-bit COL, 32-bit data, Run mode. +# ESDCTL_ESDCTL1: idem. +DATA 4 0x83FD9000 0xb2a20000 +DATA 4 0x83FD9008 0xb2a20000 + +# ESDMISC: ODT off, A10 is precharge, +# Diff_DQS, AUTO_DLL_PAUSE, Bank-interleave, RALAT=1, +# 8-bank, MIF3-mode = 3, DDR2_EN +DATA 4 0x83FD9010 0x000ad6d0 + +# ESDCTL_ESDGPR: DQS-in gating on, 1/2 cycle. +DATA 4 0x83FD9034 0x90000000 + +# ESDCTL_ESDSCR: Normal operation. +DATA 4 0x83FD9014 0x00000000 diff --git a/board/Protonic/prtlvt2/prtlvt2.c b/board/Protonic/prtlvt2/prtlvt2.c new file mode 100644 index 0000000..7853a03 --- /dev/null +++ b/board/Protonic/prtlvt2/prtlvt2.c @@ -0,0 +1,513 @@ +/* + * Copyright (c) 2010 Protonic Holland + * + * Author: David Jander + * + * Based on: mx51evk.c + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "prtlvt2.h" + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; +struct io_board_ctrl *mx51_io_board; + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {MMC_SDHC2_BASE_ADDR, 1}, +}; +#endif + +typedef struct { + int pin; + int muxconf; + int padconf; + int input; + int inconf; +} ioconf_t; + +#define POUT_HS (PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST) +#define POUT_MS (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST) +#define POUT_LS (PAD_CTL_DRV_MEDIUM) +#define PIN_HYS (PAD_CTL_HYS_ENABLE) +#define PIN_HYS_PULL (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL) +#define PIN_HYS_KEEP (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE) +#define PIO_OD (PIN_HYS_PULL | PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_MEDIUM) + +static const ioconf_t const other_io_conf[] = { + /* ITU656 Video Input */ + {MX51_PIN_CSI1_D12, IOMUX_CONFIG_SION, PIN_HYS, -1, -1}, + {MX51_PIN_CSI1_D13, IOMUX_CONFIG_SION, PIN_HYS, -1, -1}, + {MX51_PIN_CSI1_D14, IOMUX_CONFIG_SION, PIN_HYS, -1, -1}, + {MX51_PIN_CSI1_D15, IOMUX_CONFIG_SION, PIN_HYS, -1, -1}, + {MX51_PIN_CSI1_D16, IOMUX_CONFIG_SION, PIN_HYS, -1, -1}, + {MX51_PIN_CSI1_D17, IOMUX_CONFIG_SION, PIN_HYS, -1, -1}, + {MX51_PIN_CSI1_D18, IOMUX_CONFIG_SION, PIN_HYS, -1, -1}, + {MX51_PIN_CSI1_D19, IOMUX_CONFIG_SION, PIN_HYS, -1, -1}, + {MX51_PIN_CSI1_PIXCLK, -1, PIN_HYS, -1, -1}, + + /* nPCTS_INT: GPIO11 on USBH1_DATA0 */ + {MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT2, PIN_HYS_PULL, -1, -1}, + + /* SCL_2V8, SDA_2V8 on KEY_COL4 and KEY_COL5 */ + {MX51_PIN_KEY_COL4, IOMUX_CONFIG_ALT3, PIO_OD, MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, INPUT_CTL_PATH1}, + {MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT3, PIO_OD, MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, INPUT_CTL_PATH1}, + + /* SCL_1V8, SDA_1V8 on EIM_D16 and EIM_D19 */ + {MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT4, PIO_OD, MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, INPUT_CTL_PATH0}, + {MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT4, PIO_OD, MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, INPUT_CTL_PATH0}, + + /* GPIO1 group */ + {MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1, PIN_HYS_PULL | PAD_CTL_22K_PU, -1, -1}, /* CAN1_nINT */ + {MX51_PIN_GPIO1_1, IOMUX_CONFIG_ALT1, POUT_LS, -1, -1}, /* CAN1_TERM */ + {MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0, POUT_LS, -1, -1}, /* BLEN */ + {MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT0, PIN_HYS_PULL | PAD_CTL_22K_PU, -1, -1}, /* CAN2_nINT */ + {MX51_PIN_GPIO1_4, IOMUX_CONFIG_ALT2, POUT_LS, -1, -1}, /* WDOG */ + {MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0, PIN_HYS_PULL | PAD_CTL_22K_PU, -1, -1}, /* nLVDS_PDN */ + {MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0, PIN_HYS_PULL | PAD_CTL_22K_PU, -1, -1}, /* nUSD_CD */ + {MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0, POUT_LS, -1, -1}, /* nITU656_PDN */ + {MX51_PIN_GPIO1_8, IOMUX_CONFIG_ALT0, PIN_HYS, -1, -1}, /* PMIC_INT */ + {MX51_PIN_GPIO1_9, IOMUX_CONFIG_ALT0, PIN_HYS_PULL | PAD_CTL_22K_PU, -1, -1}, /* JN4148_INT */ + + /* LCD Display */ + {MX51_PIN_DI1_DISP_CLK, -1, POUT_MS, -1, -1}, + + { -1, -1, -1, -1, -1} +}; + +u32 get_board_rev(void) +{ + return system_rev; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + return 0; +} + +static void setup_iomux_uart(void) +{ + unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; + + /* Uart1 */ + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); + + /* Uart2 */ + mxc_request_iomux(MX51_PIN_UART2_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART2_RXD, pad | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_UART2_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART2_TXD, pad | PAD_CTL_SRE_FAST); +} + +static void setup_iomux_fec(void) +{ + /*FEC_MDIO*/ + mxc_request_iomux(MX51_PIN_DI2_PIN3, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DI2_PIN3, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH /* | PAD_CTL_ODE_OPENDRAIN_ENABLE */ | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); /* OD, 22k-PU */ + mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, INPUT_CTL_PATH1); + + /*FEC_MDC*/ + mxc_request_iomux(MX51_PIN_DI2_PIN2, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DI2_PIN2, PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* FEC RDATA[3] */ + mxc_request_iomux(MX51_PIN_DISP2_DAT0, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT0, PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, INPUT_CTL_PATH1); + + /* FEC RDATA[2] */ + mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DI_GP4, PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, INPUT_CTL_PATH1); + + /* FEC RDATA[1] */ + mxc_request_iomux(MX51_PIN_DI2_DISP_CLK, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, INPUT_CTL_PATH1); + + /* FEC RDATA[0] */ + mxc_request_iomux(MX51_PIN_DISP2_DAT14, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT14, PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, INPUT_CTL_PATH1); + + /* FEC TDATA[3] */ + mxc_request_iomux(MX51_PIN_DISP2_DAT8, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT8, PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* FEC TDATA[2] */ + mxc_request_iomux(MX51_PIN_DISP2_DAT7, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT7, PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* FEC TDATA[1] */ + mxc_request_iomux(MX51_PIN_DISP2_DAT6, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT6, PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* FEC TDATA[0] */ + mxc_request_iomux(MX51_PIN_DISP2_DAT15, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT15, PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* FEC TX_EN */ + mxc_request_iomux(MX51_PIN_DISP2_DAT9, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT9, PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* FEC TX_ER */ + mxc_request_iomux(MX51_PIN_DI_GP3, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DI_GP3, PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* FEC TX_CLK */ + mxc_request_iomux(MX51_PIN_DISP2_DAT13, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT13, PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + mxc_iomux_set_input(MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, INPUT_CTL_PATH1); + + /* FEC TX_COL */ + mxc_request_iomux(MX51_PIN_DISP2_DAT10, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT10, PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + mxc_iomux_set_input(MUX_IN_FEC_FEC_COL_SELECT_INPUT, INPUT_CTL_PATH1); + + /* FEC RX_CLK */ + mxc_request_iomux(MX51_PIN_DISP2_DAT11, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT11, PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, INPUT_CTL_PATH1); + + /* FEC RX_CRS */ + mxc_request_iomux(MX51_PIN_DI2_PIN4, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DI2_PIN4, PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + mxc_iomux_set_input(MUX_IN_FEC_FEC_CRS_SELECT_INPUT, INPUT_CTL_PATH1); + + /* FEC RX_ER */ + mxc_request_iomux(MX51_PIN_DISP2_DAT1, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT1, PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, INPUT_CTL_PATH1); + + /* FEC RX_DV */ + mxc_request_iomux(MX51_PIN_DISP2_DAT12, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_DISP2_DAT12, PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, INPUT_CTL_PATH1); +} + +#ifdef CONFIG_MXC_SPI +static void setup_iomux_spi(void) +{ + /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ + mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, PAD_CTL_HYS_ENABLE | PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, PAD_CTL_HYS_ENABLE | PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* Select mux mode: ALT0 mux port: of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, PAD_CTL_HYS_ENABLE | PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */ + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, PAD_CTL_HYS_ENABLE | PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */ + // mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); + // mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180); + + /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, PAD_CTL_HYS_ENABLE | PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* CSPI1_SS2 on DI1_PIN11 : ALT7 */ + mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7); + mxc_iomux_set_pad(MX51_PIN_DI1_PIN11, PAD_CTL_HYS_ENABLE | PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* CSPI1_SS3 on USBH1_DATA7 : ALT1 */ + mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, PAD_CTL_HYS_ENABLE | PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); +} +#endif + +static void setup_iomux_ac97(void) +{ + /* AC97_BCLK: AUD5_RXC on pad SD1_CLK */ + mxc_request_iomux(MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU); + mxc_iomux_set_input(MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, INPUT_CTL_PATH1); + + /* AC97_TXD: AUD5_TXD on pad SD1_DATA0 */ + mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH); + + /* AC97_RXD: AUD5_RXD on pad SD1_DATA1 */ + mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU); + mxc_iomux_set_input(MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, INPUT_CTL_PATH2); + + /* AC97_SYNC: AUD5_TXFS on pad SD1_DATA3 */ + mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU); + mxc_iomux_set_input(MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, INPUT_CTL_PATH2); +} + +static void power_init(void) +{ + unsigned int val; + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; + + /* First of all, set SWILIMB (MC13892 errata 8690 & 8732) */ + val = pmic_reg_read(REG_SW_4); + val |= SWILIMB; + pmic_reg_write(REG_SW_4, val); + + /* Disable Power Gate 2: Enable 1V8 peripheral power */ + val = pmic_reg_read(REG_POWER_MISC); + val &= ~PWGT2SPIEN; + pmic_reg_write(REG_POWER_MISC, val); + + /* Write needed to update Charger 0 */ + /* Charge voltage=4.2V, Current=full-on, Plim=800mW, charger sw, battfet off */ + pmic_reg_write(REG_CHARGE, VCHRG0 | VCHRG1 /*| VCHRG2 */ | + ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | FETOVRD | + PLIM0 /* | PLIM1 */ | + CHRGLEDEN | CHGAUTOB | CYCLB); + + /* Configure Power Control, enable PWRON switches */ + pmic_reg_write(REG_POWER_CTL2, RESTARTEN | + PWRON1RSTEN | PWRON2RSTEN | PWRON3RSTEN | + PWRON1DBNC0 | PWRON2DBNC0 | PWRON3DBNC0 | + WDIRESET | STBYDLY0); + + /* power up the system first */ + // FIXME: Is this bit still there in rev 2? + // This bit was called PWUP?? + pmic_reg_write(REG_POWER_MISC, GPO4ADIN); + + /* Set core voltage to 1.1V */ + val = pmic_reg_read(REG_SW_0); + val = (val & (~0x80001F)) | 0x14; + pmic_reg_write(REG_SW_0, val); + + /* Setup VCC (SW2) to 1.225 */ + val = pmic_reg_read(REG_SW_1); + val = (val & (~0x80001F)) | 0x19; + pmic_reg_write(REG_SW_1, val); + + /* Setup 1V2_DIG1 (SW3) to 1.2 */ + val = pmic_reg_read(REG_SW_2); + val = (val & (~0x80001F)) | 0x18; + pmic_reg_write(REG_SW_2, val); + udelay(50); + + /* Raise the core frequency to 800MHz */ + /* printf("Core at 400 MHz!\n"); */ + /* writel(0x1, &mxc_ccm->cacrr); */ + writel(0x0, &mxc_ccm->cacrr); + + /* Set switchers in Auto in NORMAL mode & STANDBY mode */ + /* Setup the switcher mode for SW1 & SW2*/ + val = pmic_reg_read(REG_SW_4); + val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | + (SWMODE_MASK << SWMODE2_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); + pmic_reg_write(REG_SW_4, val); + + /* Setup the switcher mode for SW3 & SW4 */ + val = pmic_reg_read(REG_SW_5); + val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | + (SWMODE_MASK << SWMODE4_SHIFT) | (1<<20))); // SWBSTEN=0 ! + val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) | SWILIMB; + pmic_reg_write(REG_SW_5, val); + +#if 0 /* FIXME: This shouldn't be changed for PRTLVT2 */ + /* Set VDIG to 1.25V, VGEN3 to 1.8V, VCAM to 2.6V */ + val = pmic_reg_read(REG_SETTING_0); + val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); + val |= VDIG_1_25 | VGEN3_1_8 | VCAM_2_6; + pmic_reg_write(REG_SETTING_0, val); +#endif + + /* Set VVIDEO and VAUDIO to 2.775V */ + val = pmic_reg_read(REG_SETTING_1); + val &= ~(VVIDEO_MASK | VAUDIO_MASK); + val |= VAUDIO_2_775 | VVIDEO_2_775; + pmic_reg_write(REG_SETTING_1, val); + udelay(200); + + /* Enable VAUDIO, VVIDEO regulators */ + /* FIXME: Standby mode ? */ + val = VVIDEOEN | VAUDIOEN; + pmic_reg_write(REG_MODE_1, val); + udelay(500); + + /* Turn on backlight */ + val = readl(GPIO1_BASE_ADDR + 0x0); + val |= 0x00000004; /* Make GPIO1_2 high (BLEN) */ + writel(val, GPIO1_BASE_ADDR + 0x0); + + val = readl(GPIO1_BASE_ADDR + 0x4); + val |= 0x00000004; /* configure GPIO line as output */ + writel(val, GPIO1_BASE_ADDR + 0x4); +} + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + *cd = readl(GPIO1_BASE_ADDR) & 0x40; + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + + mxc_request_iomux(MX51_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD2_CMD, + PAD_CTL_DRV_VOT_HIGH | PAD_CTL_PUE_PULL | PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU | PAD_CTL_DRV_MAX); + mxc_iomux_set_pad(MX51_PIN_SD2_CLK, + PAD_CTL_DRV_VOT_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU | PAD_CTL_DRV_MAX); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, + PAD_CTL_DRV_VOT_HIGH | PAD_CTL_PUE_PULL | PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU | PAD_CTL_DRV_MAX); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, + PAD_CTL_DRV_VOT_HIGH | PAD_CTL_PUE_PULL | PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU | PAD_CTL_DRV_MAX); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, + PAD_CTL_DRV_VOT_HIGH | PAD_CTL_PUE_PULL | PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU | PAD_CTL_DRV_MAX); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, + PAD_CTL_DRV_VOT_HIGH | PAD_CTL_PUE_PULL | PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU | PAD_CTL_DRV_MAX); + mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_HYS_ENABLE); + status = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + + return status; +} +#endif + +int board_init(void) +{ + int t; + system_rev = get_cpu_rev(); + + gd->bd->bi_arch_number = MACH_TYPE_PRTLVT2; + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + setup_iomux_uart(); + setup_iomux_fec(); + setup_iomux_ac97(); + + /* Setup other io's */ + for(t=0; other_io_conf[t].pin>=0; t++) { + mxc_iomux_set_pad(other_io_conf[t].pin, other_io_conf[t].padconf); + if(other_io_conf[t].muxconf>=0) + mxc_request_iomux(other_io_conf[t].pin, other_io_conf[t].muxconf); + if(other_io_conf[t].input>=0) + mxc_iomux_set_input(other_io_conf[t].input, other_io_conf[t].inconf); + } + + return 0; +} + +#ifdef BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_MXC_SPI + setup_iomux_spi(); + power_init(); +#endif + return 0; +} +#endif + +int checkboard(void) +{ + puts("Board: PRTLVT2 "); + + switch (system_rev & 0xff) { + case CHIP_REV_3_0: + puts("3.0 ["); + break; + case CHIP_REV_2_5: + puts("2.5 ["); + break; + case CHIP_REV_2_0: + puts("2.0 ["); + break; + case CHIP_REV_1_1: + puts("1.1 ["); + break; + case CHIP_REV_1_0: + default: + puts("1.0 ["); + break; + } + + switch (__raw_readl(SRC_BASE_ADDR + 0x8)) { + case 0x0001: + puts("POR"); + break; + case 0x0009: + puts("RST"); + break; + case 0x0010: + case 0x0011: + puts("WDOG"); + break; + default: + puts("unknown"); + } + puts("]\n"); + return 0; +} diff --git a/board/Protonic/prtlvt2/prtlvt2.h b/board/Protonic/prtlvt2/prtlvt2.h new file mode 100644 index 0000000..2854e71 --- /dev/null +++ b/board/Protonic/prtlvt2/prtlvt2.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BOARD_FREESCALE_MX51_EVK_H__ +#define __BOARD_FREESCALE_MX51_EVK_H__ + +#ifndef __ASSEMBLY__ +struct io_board_ctrl { + u16 led_ctrl; /* 0x00 */ + u16 resv1[0x03]; + u16 sb_stat; /* 0x08 */ + u16 resv2[0x03]; + u16 int_stat; /* 0x10 */ + u16 resv3[0x07]; + u16 int_rest; /* 0x20 */ + u16 resv4[0x0B]; + u16 int_mask; /* 0x38 */ + u16 resv5[0x03]; + u16 id1; /* 0x40 */ + u16 resv6[0x03]; + u16 id2; /* 0x48 */ + u16 resv7[0x03]; + u16 version; /* 0x50 */ + u16 resv8[0x03]; + u16 id3; /* 0x58 */ + u16 resv9[0x03]; + u16 sw_reset; /* 0x60 */ +}; +#endif + +#endif diff --git a/boards.cfg b/boards.cfg index b82f530..f3f9f02 100644 --- a/boards.cfg +++ b/boards.cfg @@ -46,6 +46,7 @@ pm9263 arm arm926ejs - ronetix at91 suen3 arm arm926ejs km_arm keymile kirkwood rd6281a arm arm926ejs - Marvell kirkwood mx51evk arm armv7 mx51evk freescale mx51 +prtlvt2 arm armv7 prtlvt2 Protonic mx51 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/prtlvt2.h b/include/configs/prtlvt2.h new file mode 100644 index 0000000..bef65b1 --- /dev/null +++ b/include/configs/prtlvt2.h @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2010, Protonic Holland + * + * Author: David Jander + * + * Based on mx51evk.h: Configuration settings for the MX51EVK Board + * Copyright (C) 2007, Guennadi Liakhovetski + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + + /* High Level Configuration Options */ + +#define CONFIG_MX51 /* in a mx51 */ +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ +#define CONFIG_MX51_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_L2_OFF + +/* + * Disabled for now due to build problems under Debian and a significant + * increase in the final file size: 144260 vs. 109536 Bytes. + */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define BOARD_LATE_INIT + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX51_UART1 + +/* + * SPI Configs + * */ +#define CONFIG_CMD_SPI + +#define CONFIG_MXC_SPI + +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 0 +#define CONFIG_FSL_PMIC_CS 3 +#define CONFIG_FSL_PMIC_CLK 2500000 +#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH) + +/* + * MMC Configs + * */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +#define CONFIG_MMC + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot_addr=0xa0000000\0" \ + "uboot=u-boot.bin\0" \ + "loadaddr=0x90800000\0" \ + "bootargs_base=setenv bootargs console=tty "\ + "console=ttymxc0,${baudrate}\0"\ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=${ipaddr} nfsroot=${nfsserverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootcmd_SD=run bootcmd_SD1 bootcmd_SD2\0" \ + "bootcmd_SD1=run bootargs_base bootargs_SD\0" \ + "bootcmd_SD2=mmc read 0 ${loadaddr} 0x800 0x1280; bootm ${loadaddr}\0" \ + "bootargs_SD=setenv bootargs ${bootargs} mitsubishi_xga " \ + "video=mxcfb:1024x768-16M@60,bpp=16 root=/dev/mmcblk0p1 rootfstype=ext4 rootdelay=2\0" \ + "ethaddr=00:00:00:00:00:00\0" \ + "ipaddr=192.168.1.244\0" \ + "serverip=192.168.1.132\0" \ + "nfsserverip=192.168.1.160\0" \ + "nfsroot=/srv/home/david/Devel/Sandboxes/LEL/XDH/nfsroot\0" \ + "kernel=linux-2.6.31-prtlvt2.uImage\0" \ + "bootcmd=run bootcmd_SD1; tftpboot ${loadaddr} ${kernel}; bootm\0" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x90000000 +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_CMDLINE_EDITING + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) + +#define CONFIG_SYS_DDR_CLKSEL 0 +#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_IS_NOWHERE + +#endif