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Tue, 20 Aug 2024 02:38:28 -0700 (PDT) Received: from localhost.localdomain ([103.97.165.210]) by smtp.googlemail.com with ESMTPSA id 5614622812f47-3dd33d3fe91sm2795674b6e.9.2024.08.20.02.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Aug 2024 02:38:28 -0700 (PDT) From: Mayuresh Chitale To: u-boot@lists.denx.de Cc: Mayuresh Chitale , Rick Chen , Leo , Tom Rini , Heinrich Schuchardt , Kongyang Liu , Randolph , Michal Simek , Yu Chien Peter Lin , Ben Dooks , Samuel Holland , Dan Carpenter , Bin Meng , =?utf-8?q?=C5=81ukasz_Stelmach?= Subject: [PATCH v1 0/3] Risc-V cache operations Date: Tue, 20 Aug 2024 09:37:49 +0000 Message-Id: <20240820093800.5436-1-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This patchset adds support for using the CBO instructions to perform the dcache flush/inval operations for the qemu-riscv board when those are enabled. The CBO instructions are defined in the Risc-V CMO specification which can be found at the link below: https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.pdf Mayuresh Chitale (3): riscv: Add support for defining instructions riscv: cache: Add CBO instructions board: qemu-riscv: Override enable_caches arch/riscv/Kconfig | 4 ++ arch/riscv/include/asm/cache.h | 3 + arch/riscv/include/asm/insn-def.h | 42 ++++++++++++ arch/riscv/lib/cache.c | 90 +++++++++++++++++++++++++ board/emulation/qemu-riscv/qemu-riscv.c | 16 +++++ 5 files changed, 155 insertions(+) create mode 100644 arch/riscv/include/asm/insn-def.h