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[v1,0/3] Risc-V cache operations

Message ID 20240820093800.5436-1-mchitale@ventanamicro.com
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Series Risc-V cache operations | expand

Message

Mayuresh Chitale Aug. 20, 2024, 9:37 a.m. UTC 
This patchset adds support for using the CBO instructions to perform the
dcache flush/inval operations for the qemu-riscv board when those are
enabled. The CBO instructions are defined in the Risc-V CMO specification
which can be found at the link below:
https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.pdf

Mayuresh Chitale (3):
  riscv: Add support for defining instructions
  riscv: cache: Add CBO instructions
  board: qemu-riscv: Override enable_caches

 arch/riscv/Kconfig                      |  4 ++
 arch/riscv/include/asm/cache.h          |  3 +
 arch/riscv/include/asm/insn-def.h       | 42 ++++++++++++
 arch/riscv/lib/cache.c                  | 90 +++++++++++++++++++++++++
 board/emulation/qemu-riscv/qemu-riscv.c | 16 +++++
 5 files changed, 155 insertions(+)
 create mode 100644 arch/riscv/include/asm/insn-def.h