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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4256b097bd6sm46275635e9.30.2024.06.28.10.41.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 10:41:34 -0700 (PDT) From: Christian Marangi To: Lukasz Majewski , Sean Anderson , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream , Tom Rini , u-boot@lists.denx.de, John Crispin Cc: Christian Marangi Subject: [PATCH 00/12] clk: mediatek: add OPs to support OF_UPSTREAM Date: Fri, 28 Jun 2024 19:40:45 +0200 Message-ID: <20240628174114.8675-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.45.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean This series doesn't currently change anything and it does add all the additional OPs to make support of OF_UPSTREAM. While converting the mt7681/7686/7688/7623/7622 it was notice lots of discrepancy between the downstream dtsi and the upstream one and the clock ID between downstream clock ID and upstream clock ID. Upstream reference clock by names and clock are handled by the CCF (Common Clock Framework). The same can't be used here as we would quickly reach the max space allocated before relocation. The current mediatek clock driver reference all the parents and clocks with offset from the clk ID related to the different tables. Discrepancy between clock ID and the order in the clocks table cause one clock referenced for another or even crash for trying to access a clock at an offset that doesn't exist. To handle this and permit use of OF_UPSTREAM, various measure and changes are done to the mediatek clock driver to support it. This series have all the generic clock changes. Once this is merged, series for each SoC will came that will just change files in their dedicated clock driver. This is to prevent massive patch and to permit to split series, one for each SoC. As said at the start, these changes doesn't cause regression and are just expansion to the current API. Current behaviour is saved in every possible way (aside from the first 2 patch that fixes latent bugs) World compile tested in Azure Pipeline test Christian Marangi (12): clk: mediatek: return XTAL rate directly for gates with XTAL parent clk: mediatek: return XTAL rate for infrasys get_mux_rate clk: mediatek: add support for gates in clk_tree for infrasys clk: mediatek: add support for gate ID at offset clk: mediatek: add support for parent mux from different source clk: mediatek: add support for parent mux from different source for topckgen clk: mediatek: add support for gate clock to reference topckgen clock clk: mediatek: provide common clk init function for infrasys clk: mediatek: add support for remapping clock ID clk: mediatek: implement MUX_FLAGS and MUX_MIXED_FLAGS macro clk: mediatek: add support for GATEs for APMIXED OPs clk: mediatek: add support for APMIXED parent in infra MUX drivers/clk/mediatek/clk-mtk.c | 433 ++++++++++++++++++++++++--------- drivers/clk/mediatek/clk-mtk.h | 74 +++++- 2 files changed, 392 insertions(+), 115 deletions(-)