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Tue, 7 May 2024 17:18:05 +0200 (CEST) Received: from augenblix2.phytec.de (172.25.0.11) by Berlix.phytec.de (172.25.0.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Tue, 7 May 2024 17:18:05 +0200 From: Wadim Egorov To: , CC: , , , , , , , , , , , , , , , , Subject: [PATCH 0/5] *** phyCORE-AM62x: DDR detection / Inject DDR timing deltas *** Date: Tue, 7 May 2024 17:17:52 +0200 Message-ID: <20240507151757.1202825-1-w.egorov@phytec.de> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [172.25.0.11] X-ClientProxiedBy: Florix.phytec.de (172.25.0.13) To Berlix.phytec.de (172.25.0.12) X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphkeLIzCtJLcpLzFFi42JZI8nAo6vrZpVmsOiAscX7UxPZLea+OcBq caC/l9GiZa2HxcOr/hbPOpuYLS7fv8lqcelBqsWpxlYWixfH5rJb9P9/zmTx5sdZJotvW7Yx WkydtJnd4u3eTnaL7nfqDgIeaz/eZ/V4f6OV3WN2w0UWj52z7rJ7vDqwit3j7J0djB793S2s Hn8uvmP1OH5jO5PHplceAVxRXDYpqTmZZalF+nYJXBm9tw4xFnznrVixZiNTA+N7ri5GTg4J AROJ9zefs4PYQgJLmCR2rArqYuQCsh8xShw6fowRJMEmoC5xZ8M3VhBbRMBMYtHa82wgRcwC 75gk1h+eAuRwcAgLhEhc/asKUsMioCIxb/9MZhCbV8BSoqFzNyPEMnmJmZe+s0PEBSVOznzC AmIzA8Wbt85mhrAlJA6+eMEMcZC8xItLy1lgeqede80MYYdKHNm0mmkCo8AsJKNmIRk1C8mo BYzMqxiFcjOTs1OLMrP1CjIqS1KT9VJSNzGCYkyEgWsHY98cj0OMTByMhxglOJiVRHiPtpun CfGmJFZWpRblxxeV5qQWH2KU5mBREudd3RGcKiSQnliSmp2aWpBaBJNl4uCUamCUfsZ5d5d0 2BKBu70xa8uVOVtN5v25/sb95DSmHRHfp0p177FrV/WakHWt78jF6TKpBWHren999xET3fGG o2LSAbVLu21DGOd/TZO7ZbB0zeT4j5XTzONlnxpLu/WJ3S0tqzLboL86dCVnvnXIX+P09u3l CvOeBXwsipy6XFxoyWz1wz/Z4w8psRRnJBpqMRcVJwIAZTPaxZ8CAAA= X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean PHYTEC stores details about the hardware in an EEPROM on the SoM. We can utilize this information and chose the proper DDR timings accordingly. Due to the limited SRAM memory on the AM62x, the concept was to store only the DDR timings deltas and not their full set, see Patch 4 & 5. The last patch adds support for a 1 GB and 4 GB RAM variant of the phyCORE-AM62x. Patch 4 & 5 are based on https://patchwork.ozlabs.org/project/uboot/list/?series=404273 Wadim Egorov (5): board: phytec: Make AM6 SoM detection depend on I2C board: phytec: Fix function definitions in AM6x SOM detection arm: mach-k3: am625: Call do_board_detect() before DDR probing board: phytec: common: Introduce a method to inject DDR timings deltas board: phytec: am62x: Add support for 1 & 4 GB RAM variants arch/arm/mach-k3/am625_init.c | 2 + board/phytec/common/Kconfig | 2 + board/phytec/common/am6_som_detection.c | 18 +- board/phytec/common/am6_som_detection.h | 8 + board/phytec/common/k3/Makefile | 1 + board/phytec/common/k3/k3_ddrss_patch.c | 68 ++++++ board/phytec/common/k3/k3_ddrss_patch.h | 28 +++ board/phytec/phycore_am62x/MAINTAINERS | 1 + board/phytec/phycore_am62x/phycore-am62x.c | 152 ++++++++++++- board/phytec/phycore_am62x/phycore-ddr-data.h | 206 ++++++++++++++++++ configs/phycore_am62x_a53_defconfig | 4 + configs/phycore_am62x_r5_defconfig | 4 + 12 files changed, 483 insertions(+), 11 deletions(-) create mode 100644 board/phytec/common/k3/k3_ddrss_patch.c create mode 100644 board/phytec/common/k3/k3_ddrss_patch.h create mode 100644 board/phytec/phycore_am62x/phycore-ddr-data.h Tested-by: John Ma