From patchwork Mon Aug 14 16:04:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Torsten Duwe X-Patchwork-Id: 1821053 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RPfNG6pDpz1yfP for ; Tue, 15 Aug 2023 02:04:13 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 365A886679; Mon, 14 Aug 2023 18:04:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 74D9B867B4; Mon, 14 Aug 2023 18:04:08 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A3DFA807B3 for ; Mon, 14 Aug 2023 18:04:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=lst.de Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=duwe@lst.de Received: by verein.lst.de (Postfix, from userid 2005) id 9B2E067373; Mon, 14 Aug 2023 18:04:04 +0200 (CEST) To: Rick Chen , Leo Cc: Yanhong Wang , Xingyu Wu , Mason Huo , Hal Feng , Simon Glass , u-boot@lists.denx.de Subject: [PATCH 0/2] riscv: jh7110: visionfive2: fix u-boot crash due to missing timer Message-Id: <20230814160404.9B2E067373@verein.lst.de> Date: Mon, 14 Aug 2023 18:04:04 +0200 (CEST) From: duwe@lst.de (Torsten Duwe) X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Hi all, Since commit 55171aedda8, U-Boot on the visionfive2 stops at | initcall sequence 00000000fffd76f8 failed at call 00000000402192c8 (err=-19) | ### ERROR ### Please RESET the board ### This is init_sequence_r[initr_dm_devices] calling dm_timer_init, which returns ENODEV, because the riscv architectural timer got initialised at the ROM stage, but then discarded at relocation, and never again to be re-registered. A workaround hack was to allow it to register again in drivers/core/root.c line 439: if (CONFIG_IS_ENABLED(DM_EVENT) /* && !(gd->flags & GD_FLG_RELOC) */ ) { but that would defeat the purpose of the commit 55171aedda8 cleanup. However, the timer has a defined device tree binding which, when used, IMHO makes things a lot clearer. AFAIU, the timer roughly corresponds to the x86 TSC, which is defined on many x86 platforms, compare yourself: grep -r tsc_timer.dtsi arch/x86/dts vs. grep -r '"riscv,timer"' arch/riscv/dts At first I tried to create a series that converts all riscv platforms to use the DT for the CPU timer and removes the calls from the CPU driver, but this takes too long. Release early, release often -- these two patches fix the visionfive2, for a start. Others may follow and the CPU driver calls can be removed later when they are not needed any longer. Torsten Fixes: 55171aedda8 ("dm: Emit the arch_cpu_init_dm() even only before relocation") --- Torsten Duwe (2): riscv: allow riscv timer to be instantiated via device tree riscv: jh7110: enable riscv,timer in the device tree arch/riscv/dts/jh7110.dtsi | 9 +++++++++ drivers/timer/riscv_timer.c | 28 ++++++++++++++++++++++++++-- 2 files changed, 35 insertions(+), 2 deletions(-)