From patchwork Fri Nov 25 05:59:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 1708934 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=L1KWC+bJ; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4NJPMr16WPz23nk for ; Fri, 25 Nov 2022 16:59:50 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E3C268565F; Fri, 25 Nov 2022 06:59:43 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="L1KWC+bJ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 11A188565F; Fri, 25 Nov 2022 06:59:43 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 811D28565C for ; Fri, 25 Nov 2022 06:59:39 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=d-gole@ti.com Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AP5xZwn012945; Thu, 24 Nov 2022 23:59:35 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1669355975; bh=exmE4djhIrnKF5oW5lIpmJkafqWXIDYuaYJ0QBWUnUo=; h=From:To:CC:Subject:Date; b=L1KWC+bJzxYZd3QqZCENcC50fDHQcJjc1f8//3RXiMM85U+YwO1skuYpxEkCuHJ5B TjYuHtg7uwWydG4AOvV+mvrstuD4BoyAVj1gt0GUq795LFfrSnvuCj8Ysj2b8ZPA0J IoYceGso4BnDlz222Ei4VpxoIxgKVgpUlkSvwhnc= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AP5xZ6L094459 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Nov 2022 23:59:35 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 24 Nov 2022 23:59:34 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 24 Nov 2022 23:59:34 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AP5xXBU023171; Thu, 24 Nov 2022 23:59:34 -0600 From: Dhruva Gole To: Tom Rini CC: Dhruva Gole , Vignesh , Pratyush Yadav , , Subject: [PATCH V3 0/2] spi: cqspi: Fix register reads in STIG Mode Date: Fri, 25 Nov 2022 11:29:30 +0530 Message-ID: <20221125055932.398322-1-d-gole@ti.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Intent of these patches is to fix register reads in STIG mode and also use STIG mode while reading flash registers. Currently if you try to read a register while in STIG mode there is no support for ADDR and thus naturally a register never gets read from the flash. This series supercedes the previously sent: https://lore.kernel.org/u-boot/20221115114926.174351-1-d-gole@ti.com/ Logs demonstrating the usage and working of QSPI-NOR Flash (Cypress s25hs512t) can be found on the link below: https://gist.github.com/DhruvaG2000/11e7b4ee6a381be9d86b69b2bc2616e4 change log: ---------- v3: Improvements over the last 2 versions, I have added a bit mask to make sure nbytes dont overflow bit fields. Also minor improvements in wording of comments and commit log. v2: add the setup ADDR bits patch because STIG read of registers wasn't present earlier. v1: use STIG mode if reads are small. Dhruva Gole (2): spi: cadence_qspi: setup ADDR Bits in cmd reads spi: cadence_qspi: use STIG mode for small reads drivers/spi/cadence_qspi.c | 8 +++++++- drivers/spi/cadence_qspi_apb.c | 13 +++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-)