From patchwork Fri Apr 1 08:55:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1612101 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KVDXr0GzLz9sG5 for ; Fri, 1 Apr 2022 19:55:53 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3DC0584280; Fri, 1 Apr 2022 10:55:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id EA3C68428C; Fri, 1 Apr 2022 10:55:37 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DC62A84281 for ; Fri, 1 Apr 2022 10:55:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sam.shih@mediatek.com X-UUID: 6b1f48d1f4d446e9954c7f0f0f8188a2-20220401 X-UUID: 6b1f48d1f4d446e9954c7f0f0f8188a2-20220401 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 253602451; Fri, 01 Apr 2022 16:55:16 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 1 Apr 2022 16:55:14 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 1 Apr 2022 16:55:14 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 1 Apr 2022 16:55:14 +0800 From: Sam Shih To: Tom Rini , Ryder Lee , "Weijie Gao" , Chunfeng Yun , GSS_MTK_Uboot_upstream , CC: Sam Shih Subject: [v3,0/3] Add support for different mediatek pinctrl designs Date: Fri, 1 Apr 2022 16:55:07 +0800 Message-ID: <20220401085510.28668-1-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean There are some issues with patch series v2, some of the modifications in patch 2/3 are misapplied in patch 3/3 MediaTek SoC's pinconf register usage varies by SoC, So the original code uses V0/V1 to mark different pinconf design. But actually, the real difference is the design of the "pin" itself. Different SoCs will choose specify "pin design", which we call the "io_type" of the pin. For a better understanding of mediatek pinctrl design. and make the driver clear and flexible, this patch series changes common parts of mediatek pinctrl driver to support various pinctrl controller designs. --- v3: fix v2 patch series misapplied v2: fix build fail caused by patch [2/3] Sam Shih (3): pinctrl: mediatek: rewrite mtk_pinconf_set and related functions pinctrl: mediatek: introduce multiple memory bases support pinctrl: mediatek: add support for different types of IO pins drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 219 ++++++++++++++---- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 78 ++++++- 2 files changed, 246 insertions(+), 51 deletions(-)