From patchwork Tue Apr 13 09:31:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Green Wan X-Patchwork-Id: 1465670 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FKL426LHTz9sSC for ; Tue, 13 Apr 2021 19:32:32 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8BA79819D9; Tue, 13 Apr 2021 11:32:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 52FE081A04; Tue, 13 Apr 2021 11:32:16 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from transporter.internal.sifive.com (unknown [64.62.193.209]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0887B819D2 for ; Tue, 13 Apr 2021 11:32:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=green.wan@sifive.com Received: from gamma15.internal.sifive.com (gamma15.internal.sifive.com [10.14.21.64]) by transporter.internal.sifive.com (Postfix) with ESMTPS id 57254203C0; Tue, 13 Apr 2021 02:32:11 -0700 (PDT) Received: from localhost (gamma15.internal.sifive.com [local]) by gamma15.internal.sifive.com (OpenSMTPD) with ESMTPA id 9c3b00ed; Tue, 13 Apr 2021 09:32:11 +0000 (UTC) From: Green Wan To: Cc: Green Wan , Rick Chen , Paul Walmsley , Pragnesh Patel , Sean Anderson , Bin Meng , Simon Glass , Atish Patra , Leo Yu-Chi Liang , Brad Kim , u-boot@lists.denx.de (open list) Subject: [RFC PATCH v5 0/2] arch: riscv: cpu: Add callback to init each core Date: Tue, 13 Apr 2021 02:31:55 -0700 Message-Id: <20210413093157.458526-1-green.wan@sifive.com> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Add a callback interface, harts_early_init() to perform riscv CPU hart-dependent configuration for each hart. harts_early_init() is placed after stack of harts are initialized and before main boot hart is picked up. Several conditions should be aware of or avoided are listed: - cannot access gd At the moment, gd hasn't initialized yet. - all operations in harts_early_init() should only affect core itself For example, the operations for board level should be moved to mach_xxx() or board_init_xxx() functions instead. - Common resource need protection if multicore Since all harts might enter harts_early_init() in parallel, common resource need a mechanism to handle race condition. - A reference implementation is added in ./arch/riscv/cpu/cpu.c The implementation is declared with '__weak' and can be overridden. Changelogs: v5 - rename riscv_hart_early_init to harts_early_init - rephrase dummy for harts_early_init() to callback but keep current comments not specific for customizing CSRs only. - Fix nit in [2/2] and add reviewed-by v4 - Revising the comments for riscv_hart_early_init() in [1/2] - Remove unnecessary braces and add reviewed-by in [2/2] Green Wan (2): arch: riscv: cpu: Add callback to init each core board: sifive: unmatched: clear feature disable CSR arch/riscv/cpu/cpu.c | 15 +++++++++++++++ arch/riscv/cpu/start.S | 14 ++++++++++++++ board/sifive/unmatched/spl.c | 15 +++++++++++++++ 3 files changed, 44 insertions(+)