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From: Pratyush Yadav
To: Jagan Teki , Vignesh Raghavendra
CC: Pratyush Yadav , , Sekhar Nori
, Pragnesh Patel
Subject: [PATCH v4 00/20] mtd: spi-nor-core: add xSPI Octal DTR support
Date: Fri, 22 May 2020 18:14:49 +0530
Message-ID: <20200522124509.6901-1-p.yadav@ti.com>
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Hi,
This series adds support for octal DTR flashes in the spi-nor framework,
and then adds hooks for the Cypress Semper flash which is an xSPI
compliant Octal DTR flash.
The Cadence QSPI controller driver is also updated to run in Octal DTR
mode.
Tested on TI J721e EVM.
Changes in v4:
- Fix BFPT parsing stopping too early for JESD216 rev B flashes.
- Instead of just checking for spi_nor_get_protocol_width() in
spi_nor_octal_dtr_enable(), make sure the protocol is
SNOR_PROTO_8_8_8_DTR since get_protocol_width() only cares about data
width.
- Do not enable stateful X-X-X modes if the reset line is broken.
- Instead of setting SNOR_READ_HWCAPS_8_8_8_DTR from Profile 1.0 table
parsing, do it in spi_nor_info_init_params() instead based on the
SPI_NOR_OCTAL_DTR_READ flag instead.
- Set SNOR_HWCAPS_PP_8_8_8_DTR in s28hs post_sfdp hook since this
capability is no longer set in Profile 1.0 parsing.
- Rename spi_nor_cypress_octal_enable() to
spi_nor_cypress_octal_dtr_enable().
- Instead of hard-coding 8D-8D-8D Fast Read dummy cycles to 20, find
them out from the Profile 1.0 table.
- Call post-bfpt fixup when exiting early because of JESD rev A.
- Do not make an invalid Quad Enable BFPT field a fatal error. Silently
ignore it by assuming no quad enable bit is present.
- Set cmd.nbytes to 1 when using SPI_MEM_OP_CMD().
- Reject ops with more than 1 command byte in
spi_mem_default_supports_op().
- Drop flag SPI_NOR_SOFT_RESET. Instead, discover soft reset capability
via BFPT.
- Add missing headers that were removed from common header.
Changes in v3:
- Read 2 bytes in Octal DTR mode when reading SR and FSR to avoid
tripping up controllers.
- Use op->data.nbytes as a measure of whether the data phase exists or
not. This fixes data buswidth not being updadted for SR and FSR reads
because they keep data buffer as NULL when calling spi_nor_setup_op().
- Add support for Micron mt35xu512aba to run in Octal DTR mode.
Pratyush Yadav (20):
spi: spi-mem: allow specifying whether an op is DTR or not
spi: spi-mem: allow specifying a command's extension
spi: cadence-qspi: Do not calibrate when device tree sets read delay
spi: cadence-qspi: Add support for octal DTR flashes
mtd: spi-nor-core: Add a ->setup() hook
mtd: spi-nor-core: Move SFDP related declarations to top
mtd: spi-nor-core: Introduce flash-specific fixup hooks
mtd: spi-nor-core: Rework hwcaps selection
mtd: spi-nor-core: Add support for DTR protocol
mtd: spi-nor-core: prepare BFPT parsing for JESD216 rev D
mtd: spi-nor-core: Get command opcode extension type from BFPT
mtd: spi-nor-core: Parse xSPI Profile 1.0 table
mtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode
mtd: spi-nor-core: Enable octal DTR mode when possible
mtd: spi-nor-core: Do not make invalid quad enable fatal
mtd: spi-nor-core: Detect Soft Reset sequence support from BFPT
mtd: spi-nor-core: Perform a Soft Reset on shutdown
mtd: spi-nor-core: Perform a Soft Reset on boot
mtd: spi-nor-core: Add support for Cypress Semper flash
mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode
drivers/mtd/spi/Kconfig | 11 +
drivers/mtd/spi/sf_internal.h | 12 +
drivers/mtd/spi/sf_probe.c | 9 +
drivers/mtd/spi/spi-nor-core.c | 1253 ++++++++++++++++++++++++++------
drivers/mtd/spi/spi-nor-ids.c | 4 +-
drivers/mtd/spi/spi-nor-tiny.c | 22 -
drivers/spi/cadence_qspi.c | 87 ++-
drivers/spi/cadence_qspi.h | 15 +-
drivers/spi/cadence_qspi_apb.c | 286 +++++++-
drivers/spi/spi-mem.c | 6 +
include/linux/mtd/spi-nor.h | 275 +++++--
include/spi-mem.h | 17 +-
12 files changed, 1639 insertions(+), 358 deletions(-)
---
2.26.2