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d="scan'208";a="139952068" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 18 Apr 2020 14:10:16 +0800 IronPort-SDR: jhgdNYKYl2t5lcf43tUyvnOXCfvJgN2u181iCyNvd95MMtQhCJSgoDgReFH5wiHoZBEpXtPPpR 4Fx92/dcHpiM7bwYTrFUegvwIFUOH2a80= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2020 23:00:39 -0700 IronPort-SDR: +RdtatdNxPU62Bq4OPp1hII7JhjSauqqSULqbBsLNOsE3VNu3KoZeA7SWFmUDlw3yb7++rEQ7L +QhyADDDU/5g== WDCIronportException: Internal Received: from 5s19j72.ad.shared (HELO yoda.hgst.com) ([10.86.56.13]) by uls-op-cesaip01.wdc.com with ESMTP; 17 Apr 2020 23:10:15 -0700 From: Atish Patra To: u-boot@lists.denx.de Cc: Atish Patra , Anup Patel , Bin Meng , Lukas Auer , Heinrich Schuchardt , agraf@csgraf.de, ard.biesheuvel@linaro.org, Marcus Comstedt , Paul Walmsley , Rick Chen , palmer@dabbelt.com Subject: [RESEND PATCH v5 0/6] RISC-V DT related fixes for reserved memory & UEFI Date: Fri, 17 Apr 2020 23:07:52 -0700 Message-Id: <20200418060758.4839-1-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean This series adds few DT related fixes required for Linux EFI stub to work on RISC-V. Patch 1 adds the boot hartid property under /chosen node. The related discussion can be found here. https://patchwork.ozlabs.org/patch/1233664/ https://lists.denx.de/pipermail/u-boot/2020-March/402085.html Patch 2 fixes a generic issue in fdtdec related to reserved memory node. Patch 3,4,5 provide one of the option to update reserved-memory node for next stage. It depends on master OpenSBI branch. The other options are SBI extension and trap/emulate on PMP csr access. The detaild discussion can be found here. https://github.com/riscv/riscv-sbi-doc/pull/37 Patch 1 & 2 can be applied independently from 3 and 4. I want to keep all the patches together to provide a holistic view of changes required for RISC-V UEFI. Changes v4->v5: 1. Added comments for new functions. Changes v3->v4: 1. Dropped generic efi fix patch as it is already merged. 2. Moved all the fdt fixups to a common file. 3. Addressed few nit comments. Changes from v2->v3: 1. Update the DT meant for OS if it is different from the one used by U-Boot 2. Use different FDT api to obtain "reg" address & size to honor the cell count. Changes from v1->v2: 1. Fix the issue if chosen node is not present. Changes from previous version: 1. Renamed the DT node property to "boot-hartid" from "efi-boot-hartid". 2. Changed the property type to u32 instead of u64 for RV32 compatibility. Atish Patra (6): riscv: Add boot hartid to Device tree fdtdec: Fix boundary check riscv: Provide a mechanism to fix DT for reserved memory riscv: Setup reserved-memory node for FU540 riscv: Copy the reserved-memory nodes to final DT riscv: Move all fdt fixups together arch/riscv/cpu/start.S | 1 + arch/riscv/include/asm/global_data.h | 1 + arch/riscv/include/asm/u-boot-riscv.h | 2 + arch/riscv/lib/Makefile | 1 + arch/riscv/lib/asm-offsets.c | 1 + arch/riscv/lib/bootm.c | 5 - arch/riscv/lib/fdt_fixup.c | 150 ++++++++++++++++++++++++++ configs/sifive_fu540_defconfig | 1 + lib/fdtdec.c | 3 +- 9 files changed, 159 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/lib/fdt_fixup.c --- 2.25.1