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From: Pratyush Yadav
To: Jagan Teki , Vignesh Raghavendra
CC: Pratyush Yadav , , Sekhar Nori
Subject: [PATCH v2 00/16] mtd: spi-nor-core: add xSPI Octal DTR support
Date: Tue, 24 Mar 2020 01:45:02 +0530
Message-ID: <20200323201519.20341-1-p.yadav@ti.com>
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Hi,
This series adds support for octal DTR flashes in the spi-nor framework,
and then adds hooks for the Cypress Semper flash which is an xSPI
compliant Octal DTR flash.
The Cadence QSPI controller driver is also updated to run in Octal DTR
mode.
Tested on TI J721e EVM with 1-bit ECC on the Cypress flash on top of
u-boot-ti/next.
This series depends on [0]. v1 can be found at [1].
[0] cf. <20200224071051.19331-1-p.yadav@ti.com>
[0] https://lists.denx.de/pipermail/u-boot/2020-February/401192.html
[1] cf. <20200226125606.22684-1-p.yadav@ti.com>
[1] https://lists.denx.de/pipermail/u-boot/2020-February/401414.html
Changes in v2:
- Update the series with comments received on the corresponding kernel
series.
- Drop the DT properties "spi-rx-dtr" and "spi-tx-dtr". Instead, if
later a need is felt to disable DTR in case someone has a board with
Octal DTR capable flash but does not support DTR transactions for some
reason, a property like "spi-no-dtr" can be added.
- Remove mode bits SPI_RX_DTR and SPI_TX_DTR.
- Rename 'is_dtr' to 'dtr'.
- Make 'dtr' a bitfield.
- Reject DTR ops in spi_mem_default_supports_op().
- Perform a Software Reset on flashes that support it when shutting
down.
- Perform a Software Reset on boot if enabled.
- Drop enum 'spi_mem_cmd_ext' and make command opcode u16 instead.
Update spi-nor to use the 2-byte command instead of the command
extension. Since we still need a "extension type", mode that enum to
spi-nor and name it 'spi_nor_cmd_ext'.
- Rework hwcaps selection to use supports_op() instead of relying on
mode bits.
- Fix a build failure when SFDP is not enabled.
- Read CFR3V instead of CFR3N in the s28hs setup hook. Reading CFR3N
means we need to know beforehand how many dummy cycles are needed.
Reading CFR3V doesn't need that because the dummy cycles are exactly
the same as the Read ID cycles. So if we can Read ID we can read
volatile registers.
Pratyush Yadav (16):
spi: spi-mem: allow specifying whether an op is DTR or not
spi: spi-mem: allow specifying a command's extension
spi: cadence-qspi: Do not calibrate when device tree sets read delay
spi: cadence-qspi: Add support for octal DTR flashes
mtd: spi-nor-core: Add a ->setup() hook
mtd: spi-nor-core: Move SFDP related declarations to top
mtd: spi-nor-core: Introduce flash-specific fixup hooks
mtd: spi-nor-core: Rework hwcaps selection
mtd: spi-nor-core: Add support for DTR protocol
mtd: spi-nor-core: Get command opcode extension type from BFPT
mtd: spi-nor-core: Parse xSPI Profile 1.0 table
mtd: spi-nor-core: Use Read SR dummy cycle and address width from SFDP
mtd: spi-nor-core: Enable octal DTR mode when possible
mtd: spi-nor-core: Perform a Soft Reset on shutdown
mtd: spi-nor-core: Perform a Soft Reset on boot
mtd: spi-nor-core: Add support for Cypress Semper flash
drivers/mtd/spi/Kconfig | 11 +
drivers/mtd/spi/sf_internal.h | 9 +
drivers/mtd/spi/sf_probe.c | 9 +
drivers/mtd/spi/spi-nor-core.c | 1166 ++++++++++++++++++++++++--------
drivers/mtd/spi/spi-nor-ids.c | 1 +
drivers/mtd/spi/spi-nor-tiny.c | 22 -
drivers/spi/cadence_qspi.c | 87 ++-
drivers/spi/cadence_qspi.h | 15 +-
drivers/spi/cadence_qspi_apb.c | 286 +++++++-
drivers/spi/spi-mem.c | 3 +
include/linux/mtd/spi-nor.h | 261 +++++--
include/spi-mem.h | 16 +-
12 files changed, 1497 insertions(+), 389 deletions(-)
---
2.25.0