From patchwork Wed Aug 7 21:12:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 1143956 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4644Yh0sPHz9s7T for ; Thu, 8 Aug 2019 20:36:56 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id BBF0EC21EC3; Thu, 8 Aug 2019 10:36:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 64049C21E3B; Thu, 8 Aug 2019 10:36:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4CA28C21E49; Wed, 7 Aug 2019 21:12:59 +0000 (UTC) Received: from mail-edgeS23.fraunhofer.de (mail-edges23.fraunhofer.de [153.97.7.23]) by lists.denx.de (Postfix) with ESMTPS id 3C3FAC21E13 for ; Wed, 7 Aug 2019 21:12:58 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2HrKwB5Pktd/xoBYJlmHgEGBwaBZ4IYbVIBW4dohTKGS4MNgTMBmFQJAQEBAQEBAQEBCB8QAQGBBIM7glUjOBMBBAEBBQEBAgEKAgJphScMhC9fdgFBBYEeIA6DJwGCCQGtGoN2hQaBSQkBgSqHC4RZgVc/gRABgl2LGgSOVpxWBwKBOWVdBIV8jToMG4IwixSKbo8Bkk+EGYFnIoFYMxokgzsJiWiHFz0BMo8hAQE X-IPAS-Result: A2HrKwB5Pktd/xoBYJlmHgEGBwaBZ4IYbVIBW4dohTKGS4MNgTMBmFQJAQEBAQEBAQEBCB8QAQGBBIM7glUjOBMBBAEBBQEBAgEKAgJphScMhC9fdgFBBYEeIA6DJwGCCQGtGoN2hQaBSQkBgSqHC4RZgVc/gRABgl2LGgSOVpxWBwKBOWVdBIV8jToMG4IwixSKbo8Bkk+EGYFnIoFYMxokgzsJiWiHFz0BMo8hAQE X-IronPort-AV: E=Sophos;i="5.64,358,1559512800"; d="scan'208";a="12425728" Received: from mail-mtaka26.fraunhofer.de ([153.96.1.26]) by mail-edgeS23.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Aug 2019 23:12:33 +0200 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0CLDAAbPktdfRBhWMBmHgEGBwaBZ4MFUiA8jRqJWJoICQEDAQEBAQEIHxABAYQ/gnc4EwEEAQEEAQEDAQoUAQEWOoUuDIYDAUEFgR4gDoMnAYIKrRqIfIFJCQGBKocLhjA/gRABgl2LGgSOVpxWBwKBOWVdBIV8jToMG4IwixSKbo8BlmiBZyCBWTMaJIM7CYlohxc9AzCPIQEB X-IronPort-AV: E=Sophos;i="5.64,358,1559512800"; d="scan'208";a="52930261" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP11EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA26.fraunhofer.de with ESMTP/TLS/AES256-SHA; 07 Aug 2019 23:12:32 +0200 Received: from localhost.de (10.80.233.50) by FGDEMUCIMP11EXC.ads.fraunhofer.de (10.80.232.42) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 7 Aug 2019 23:15:10 +0200 From: Lukas Auer To: Date: Wed, 7 Aug 2019 23:12:02 +0200 Message-ID: <20190807211213.21849-1-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24824.005 X-TM-AS-Result: No--11.158800-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-Mailman-Approved-At: Thu, 08 Aug 2019 10:36:04 +0000 Cc: Alistair Francis , Miquel Raynal , Eugeniu Rosca , Michal Simek , Marek Vasut , Marek Vasut , Tien Fong Chee , Alexander Graf , Bartosz Golaszewski , Stefan Roese , Chris Packham , Ryder Lee , Heinrich Schuchardt , Julius Werner Subject: [U-Boot] [PATCH v3 00/11] SPL support for RISC-V X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This series adds support for SPL to RISC-V U-Boot. Images can be booted via OpenSBI (FW_DYNAMIC firmware) or by directly jumping to them. In the former case, OpenSBI and U-Boot proper are bundled as a FIT image and made available to U-Boot SPL. Currently, only the QEMU board enables U-Boot SPL with a dedicated configuration. It uses RAM as SPL boot device. On many RISC-V CPUs, the device tree is provided to U-Boot by the first stage bootloader. This requires changes to U-Boot SPL (patches 1, 2 and 3), which modify the behavior on other boards as well. To test this series, OpenSBI has to be compiled first. The fw_dynamic.bin binary must be copied into the U-Boot root directory. Alternatively, the location of the binary can be specified with the OPENSBI environment variable. U-Boot can then be build as normal using the configuration qemu-riscv64_spl_defconfig for 64-bit builds or qemu-riscv32_spl_defconfig for 32-bit builds. The outputs from the build process are the U-Boot SPL binary (spl/u-boot-spl.bin) and the U-Boot FIT image (u-boot.itb) containing U-Boot proper and OpenSBI. U-Boot can be run in QEMU with the following command. qemu-system-riscv64 -nographic -machine virt -kernel spl/u-boot-spl \ -device loader,file=u-boot.itb,addr=0x80200000 Changes in v3: - Rebase on u-boot-riscv/master - Update commit message to include minimum version of OpenSBI - Rebase on u-boot/master - Add note on minimum version of OpenSBI Changes in v2: - Rebase on master and format documentation as reStructuredText Lukas Auer (11): fdtdec: make CONFIG_OF_PRIOR_STAGE available in SPL Makefile: support building SPL FIT images without device trees spl: fit: use U-Boot device tree when FIT image has no device tree riscv: add run mode configuration for SPL spl: support booting via RISC-V OpenSBI riscv: add SPL support riscv: support SPL stack and global data relocation riscv: add a generic FIT generator script riscv: set default FIT generator script and build target for SPL builds riscv: qemu: add SPL configuration doc: update QEMU RISC-V documentation Kconfig | 4 +- Makefile | 8 +- arch/Kconfig | 6 ++ arch/riscv/Kconfig | 36 +++++++-- arch/riscv/cpu/ax25/Kconfig | 6 +- arch/riscv/cpu/cpu.c | 6 +- arch/riscv/cpu/generic/Kconfig | 5 +- arch/riscv/cpu/start.S | 62 ++++++++++++++- arch/riscv/cpu/u-boot-spl.lds | 82 +++++++++++++++++++ arch/riscv/include/asm/encoding.h | 2 +- arch/riscv/include/asm/spl.h | 31 ++++++++ arch/riscv/lib/Makefile | 8 +- arch/riscv/lib/mkimage_fit_opensbi.sh | 100 ++++++++++++++++++++++++ arch/riscv/lib/spl.c | 48 ++++++++++++ board/emulation/qemu-riscv/Kconfig | 10 +++ board/emulation/qemu-riscv/MAINTAINERS | 2 + board/emulation/qemu-riscv/qemu-riscv.c | 17 ++++ common/image.c | 1 + common/spl/Kconfig | 17 ++++ common/spl/Makefile | 1 + common/spl/spl.c | 8 +- common/spl/spl_fit.c | 37 ++++++--- common/spl/spl_opensbi.c | 85 ++++++++++++++++++++ configs/qemu-riscv32_spl_defconfig | 11 +++ configs/qemu-riscv64_spl_defconfig | 12 +++ doc/board/emulation/qemu-riscv.rst | 60 +++++++++++++- include/configs/qemu-riscv.h | 14 ++++ include/fdtdec.h | 2 +- include/image.h | 1 + include/opensbi.h | 40 ++++++++++ include/spl.h | 5 ++ lib/fdtdec.c | 6 +- 32 files changed, 691 insertions(+), 42 deletions(-) create mode 100644 arch/riscv/cpu/u-boot-spl.lds create mode 100644 arch/riscv/include/asm/spl.h create mode 100755 arch/riscv/lib/mkimage_fit_opensbi.sh create mode 100644 arch/riscv/lib/spl.c create mode 100644 common/spl/spl_opensbi.c create mode 100644 configs/qemu-riscv32_spl_defconfig create mode 100644 configs/qemu-riscv64_spl_defconfig create mode 100644 include/opensbi.h