From patchwork Mon Apr 22 16:13:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1088768 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Yr+/71zk"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44nsFh0hKDz9s6w for ; Tue, 23 Apr 2019 02:18:32 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id BE0E6C21DB3; Mon, 22 Apr 2019 16:18:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2BE5BC21C4A; Mon, 22 Apr 2019 16:18:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D2436C21C4A; Mon, 22 Apr 2019 16:18:24 +0000 (UTC) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lists.denx.de (Postfix) with ESMTPS id 44EB8C21C2C for ; Mon, 22 Apr 2019 16:18:24 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x3MGIII2023461; Mon, 22 Apr 2019 11:18:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1555949898; bh=I5bWJxFrNoeeSmh5l1nk1+jXvxNMqKKk8hOuV2VhGDc=; h=From:To:CC:Subject:Date; b=Yr+/71zkfEIVhsW5tlzsfuM/Dr4haKaLebl9oY/l12XNOQAVrn5dG1QA8p5SZjkeD eWqNx5T0Veu9fJQd3OrOyp1I6Oj3scI8QACgrdilZ64659iUP6xCmXCcdd9ivdfO8h 4B9952VdQ4Gfqbm4os+JFI6GuWroyA/Dtj/NCabw= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x3MGIIOl020224 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 22 Apr 2019 11:18:18 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 22 Apr 2019 11:18:17 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 22 Apr 2019 11:18:17 -0500 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x3MGIFlK079031; Mon, 22 Apr 2019 11:18:16 -0500 From: Vignesh Raghavendra To: Albert Aribaud , Lokesh Vutla , Tom Rini Date: Mon, 22 Apr 2019 21:43:31 +0530 Message-ID: <20190422161333.5022-1-vigneshr@ti.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 0/2] Add Kconfig to disable cache ops X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This series adds a Kconfig to disable cache maintenance operations on a coherent architectures. And disable cache flush/invalidate ops for SPL/U-Boot code running on A53 core of AM654 SoC(which is IO coherent) v2: Allow flush_dcache_all() and invalidate_dcache_all() that are used before enabling/disabling dcache by U-Boot and are special case. Vignesh Raghavendra (2): arch: armv8: Provide a way to disable cache maintenance ops board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build arch/Kconfig | 9 +++++++++ arch/arm/cpu/armv8/cache_v8.c | 10 ++++++++++ board/ti/am65x/Kconfig | 1 + 3 files changed, 20 insertions(+)