From patchwork Sun Mar 17 18:28:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 1057547 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44Mnsn6qXYz9s5c for ; Mon, 18 Mar 2019 05:29:49 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8B992C21DE8; Sun, 17 Mar 2019 18:29:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 082DEC21D8E; Sun, 17 Mar 2019 18:29:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 10743C21CB6; Sun, 17 Mar 2019 18:29:12 +0000 (UTC) Received: from mail-edgeKA24.fraunhofer.de (mail-edgeka24.fraunhofer.de [153.96.1.24]) by lists.denx.de (Postfix) with ESMTPS id 99A19C21C38 for ; Sun, 17 Mar 2019 18:29:12 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2H2AAB0kY5c/xwBYJljGwEBAQEDAQEBBwMBAQGBZYIRaI4wikKcOQ0jC4Q+hFMiOBIBAQMBAQkBAwICAmkcDIJ4TWsBAQEBAQEjAg2BHAFBBYEeIA6DJwGBdAEPqlGEMAGFbwUJAYElhmmER4FXP4EQAY10A4wumCcHAoEmgSEEhRCLPgwZiwuITJB/jSuBXiKBVjMaJIM8iwuFQD4Bj2EBAQ X-IPAS-Result: A2H2AAB0kY5c/xwBYJljGwEBAQEDAQEBBwMBAQGBZYIRaI4wikKcOQ0jC4Q+hFMiOBIBAQMBAQkBAwICAmkcDIJ4TWsBAQEBAQEjAg2BHAFBBYEeIA6DJwGBdAEPqlGEMAGFbwUJAYElhmmER4FXP4EQAY10A4wumCcHAoEmgSEEhRCLPgwZiwuITJB/jSuBXiKBVjMaJIM8iwuFQD4Bj2EBAQ X-IronPort-AV: E=Sophos;i="5.58,490,1544482800"; d="scan'208";a="13835731" Received: from mail-mtaka28.fraunhofer.de ([153.96.1.28]) by mail-edgeKA24.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Mar 2019 19:29:11 +0100 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0C0AgCWkY5cfRBhWMBjHAEBAQQBAQcEAQGBZYJ5UCGNP6Z7DSOESYR0OBIBAQMBAQkBAwIUAQEWOiMMhgMBQQWBHiAOgycBgXUPqlGEMAGFbwUJAYElhmmGHj+BEAGNdAOMLpgnBwKBJoEhBIUQiz4MGYsLiEyQf40rgV4ggVczGiSDPIsLhUA+A49fAQE X-IronPort-AV: E=Sophos;i="5.58,490,1544482800"; d="scan'208";a="19588555" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP11EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA28.fraunhofer.de with ESMTP/TLS/AES256-SHA; 17 Mar 2019 19:29:10 +0100 Received: from localhost.de (10.80.233.50) by FGDEMUCIMP11EXC.ads.fraunhofer.de (10.80.232.42) with Microsoft SMTP Server (TLS) id 14.3.435.0; Sun, 17 Mar 2019 19:29:08 +0100 From: Lukas Auer To: Date: Sun, 17 Mar 2019 19:28:31 +0100 Message-ID: <20190317182842.18108-1-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24494.006 X-TM-AS-Result: No-0.667400-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Baruch Siach , Andreas Schwab , Palmer Dabbelt , Alexander Graf Subject: [U-Boot] [PATCH v3 00/11] SMP support for RISC-V X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch series adds SMP support for RISC-V to U-Boot. It allows U-Boot to run on multi-hart systems (hart is the RISC-V terminology for hardware thread). Images passed to bootm will be started on all harts. The bootm command is currently the only one that will boot images on all harts, bootefi is not yet supported. The patches have been successfully tested on both QEMU (machine and supervisor mode) and the HiFive Unleashed board (supervisor mode), using BBL and OpenSBI. Mainline QEMU requires two patches [1, 2] to run in this configuration. Patch [1] has been dropped and will be replaced with a U-Boot patch. [1]: https://patchwork.ozlabs.org/patch/1039493/ [2]: https://patchwork.ozlabs.org/patch/1039082/ Changes in v3: - Print error if riscv_send_ipi() fails - Adjust error message for failures of riscv_clear_ipi() to match error message for failures of riscv_send_ipi() - New patch to save the hart ID in register tp instead of s0 - Adjust patch to use the new location of the hart ID (register tp) - New patch to hang if relocation of secondary harts fails Changes in v2: - Remove unneeded quotes from NR_CPUS Kconfig entry - Move memory barrier from send_ipi_many() to handle_ipi() - Add check in send_ipi_many so that IPIs are only sent to available harts as indicated by the available_harts mask - Implement hart lottery to pick main hart to run U-Boot - Remove CONFIG_MAIN_HART as it is not required anymore - Register available harts in the available_harts mask - New patch to populate register a0 with the hart ID from the mhartid CSR in machine-mode - New patch to enable SMP on the SiFive FU540, which was previously sent independently Lukas Auer (11): riscv: add infrastructure for calling functions on other harts riscv: import the supervisor binary interface header file riscv: implement IPI platform functions using SBI riscv: delay initialization of caches and debug UART riscv: save hart ID in register tp instead of s0 riscv: add support for multi-hart systems riscv: boot images passed to bootm on all harts riscv: do not rely on hart ID passed by previous boot stage riscv: hang if relocation of secondary harts fails riscv: fu540: enable SMP riscv: qemu: enable SMP arch/riscv/Kconfig | 28 +++++ arch/riscv/cpu/cpu.c | 9 +- arch/riscv/cpu/start.S | 167 +++++++++++++++++++++++++-- arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/global_data.h | 6 + arch/riscv/include/asm/sbi.h | 94 +++++++++++++++ arch/riscv/include/asm/smp.h | 53 +++++++++ arch/riscv/lib/Makefile | 2 + arch/riscv/lib/asm-offsets.c | 1 + arch/riscv/lib/bootm.c | 13 ++- arch/riscv/lib/sbi_ipi.c | 25 ++++ arch/riscv/lib/smp.c | 118 +++++++++++++++++++ board/emulation/qemu-riscv/Kconfig | 1 + board/sifive/fu540/Kconfig | 1 + 14 files changed, 507 insertions(+), 12 deletions(-) create mode 100644 arch/riscv/include/asm/sbi.h create mode 100644 arch/riscv/include/asm/smp.h create mode 100644 arch/riscv/lib/sbi_ipi.c create mode 100644 arch/riscv/lib/smp.c