From patchwork Tue Mar 5 22:53:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 1052031 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44DXJs5wx1z9sBp for ; Wed, 6 Mar 2019 09:54:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7A5D3C21C38; Tue, 5 Mar 2019 22:54:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 11073C21C38; Tue, 5 Mar 2019 22:54:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F0EB0C21C3F; Tue, 5 Mar 2019 22:54:29 +0000 (UTC) Received: from mail-edgeKA24.fraunhofer.de (mail-edgeka24.fraunhofer.de [153.96.1.24]) by lists.denx.de (Postfix) with ESMTPS id 9C413C21C38 for ; Tue, 5 Mar 2019 22:54:29 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2GiAACJ/X5c/xoBYJlkHQEBBQEHBQGBUwYBCwGCD2hxjTqKa5ougXsNIwuEPoQvIjYHDQEBAwEBAwEDAgICaRwMgnhNawEBAQEBASMCDYEcAUEFgR4gDoMnAYF0AQ+sTIQvAYV7BQkBgSUBhmOERIFXP4EQAYhghRQCjBmXbgcCgSKBGgSFA4slDBmKdYgykEGMcYFOCyeBVjMaJIM8iwuFQD4BkUcBAQ X-IPAS-Result: A2GiAACJ/X5c/xoBYJlkHQEBBQEHBQGBUwYBCwGCD2hxjTqKa5ougXsNIwuEPoQvIjYHDQEBAwEBAwEDAgICaRwMgnhNawEBAQEBASMCDYEcAUEFgR4gDoMnAYF0AQ+sTIQvAYV7BQkBgSUBhmOERIFXP4EQAYhghRQCjBmXbgcCgSKBGgSFA4slDBmKdYgykEGMcYFOCyeBVjMaJIM8iwuFQD4BkUcBAQ X-IronPort-AV: E=Sophos;i="5.58,445,1544482800"; d="scan'208";a="13621760" Received: from mail-mtaka26.fraunhofer.de ([153.96.1.26]) by mail-edgeKA24.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Mar 2019 23:54:29 +0100 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0BzAADM/H5c/xBhWMBkHQEBBQEHBQGBUwYBCwGCd44rpRmBew0jhEmEUDYHDQEBAwEBAwEDAm0cDIYDAUEFgR4gDoMnAYF1D6xNhC8BhXsFCQGBJQGGY4YbP4EQAYhghRQCjBmXbgcCgSKBGgSFA4slDBmKdYgykEGMcYFOCyaBVjMaJIM8iwuFQD4DkUUBAQ X-IronPort-AV: E=Sophos;i="5.58,445,1544482800"; d="scan'208";a="33777127" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP12EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA26.fraunhofer.de with ESMTP/TLS/AES256-SHA; 05 Mar 2019 23:54:28 +0100 Received: from localhost.de (10.80.233.51) by FGDEMUCIMP12EXC.ads.fraunhofer.de (10.80.232.43) with Microsoft SMTP Server (TLS) id 14.3.435.0; Tue, 5 Mar 2019 23:56:23 +0100 From: Lukas Auer To: Date: Tue, 5 Mar 2019 23:53:22 +0100 Message-ID: <20190305225331.1353-1-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24472.002 X-TM-AS-Result: No-1.256400-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Baruch Siach , Palmer Dabbelt , Andreas Schwab , Alexander Graf , Stefan Roese Subject: [U-Boot] [PATCH v2 0/9] SMP support for RISC-V X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch series adds SMP support for RISC-V to U-Boot. It allows U-Boot to run on multi-hart systems (hart is the RISC-V terminology for hardware thread). Images passed to bootm will be started on all harts. The bootm command is currently the only one that will boot images on all harts, bootefi is not yet supported. The patches have been successfully tested on both QEMU (machine and supervisor mode) and the HiFive Unleashed board (supervisor mode), using BBL and OpenSBI. Mainline QEMU requires two patches [1, 2] to run in this configuration. [1]: https://patchwork.ozlabs.org/patch/1039493/ [2]: https://patchwork.ozlabs.org/patch/1039082/ Changes in v2: - Remove unneeded quotes from NR_CPUS Kconfig entry - Move memory barrier from send_ipi_many() to handle_ipi() - Add check in send_ipi_many so that IPIs are only sent to available harts as indicated by the available_harts mask - Implement hart lottery to pick main hart to run U-Boot - Remove CONFIG_MAIN_HART as it is not required anymore - Register available harts in the available_harts mask - New patch to populate register a0 with the hart ID from the mhartid CSR in machine-mode - New patch to enable SMP on the SiFive FU540, which was previously sent independently Lukas Auer (9): riscv: add infrastructure for calling functions on other harts riscv: import the supervisor binary interface header file riscv: implement IPI platform functions using SBI riscv: delay initialization of caches and debug UART riscv: add support for multi-hart systems riscv: boot images passed to bootm on all harts riscv: do not rely on hart ID passed by previous boot stage riscv: fu540: enable SMP riscv: qemu: enable SMP arch/riscv/Kconfig | 28 +++++ arch/riscv/cpu/cpu.c | 9 +- arch/riscv/cpu/start.S | 152 +++++++++++++++++++++++++-- arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/global_data.h | 6 ++ arch/riscv/include/asm/sbi.h | 94 +++++++++++++++++ arch/riscv/include/asm/smp.h | 53 ++++++++++ arch/riscv/lib/Makefile | 2 + arch/riscv/lib/asm-offsets.c | 1 + arch/riscv/lib/bootm.c | 13 ++- arch/riscv/lib/sbi_ipi.c | 25 +++++ arch/riscv/lib/smp.c | 116 ++++++++++++++++++++ board/emulation/qemu-riscv/Kconfig | 1 + board/sifive/fu540/Kconfig | 1 + 14 files changed, 492 insertions(+), 10 deletions(-) create mode 100644 arch/riscv/include/asm/sbi.h create mode 100644 arch/riscv/include/asm/smp.h create mode 100644 arch/riscv/lib/sbi_ipi.c create mode 100644 arch/riscv/lib/smp.c Tested-by: Anup Patel