Message ID | 20190117110356.36753-1-anup@brainfault.org |
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Headers | show
Return-Path: <u-boot-bounces@lists.denx.de> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="bax70a+p"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43gLmz4bYmz9s3l for <incoming@patchwork.ozlabs.org>; Thu, 17 Jan 2019 22:04:19 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5BC8CC2207C; Thu, 17 Jan 2019 11:04:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 73D81C21D8A; Thu, 17 Jan 2019 11:04:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 52B58C21D8A; Thu, 17 Jan 2019 11:04:11 +0000 (UTC) Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by lists.denx.de (Postfix) with ESMTPS id 9996FC21D4A for <u-boot@lists.denx.de>; Thu, 17 Jan 2019 11:04:10 +0000 (UTC) Received: by mail-pg1-f193.google.com with SMTP id j10so4315212pga.1 for <u-boot@lists.denx.de>; Thu, 17 Jan 2019 03:04:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=5uXpXBV+OrlAdQTmFu5ZT22P0Vb23q/Dhu3v7reLSeg=; b=bax70a+pXso5yDs/7Wx4AZPCcOa4+sWJADlpS1dbCIiT6Yk9ZAT0kvNdr0j8AM6Wwr jEUSP/Uyjq3h+BgsdWqwBJR+mWel6mPG3ySER6FW6/Ei3zWQdWQGNi8DK5aZiVa/QoGo cZyA4ACGNqB/kiZK7l8QZlWkM2jObSfZcQYJ83gJpQKbm9b4EDLprG34U10aBP3bJgvy 8bjz80bRP/ztSe1FBpjysL2yfniqTdy2Mz69HVhvhEHeTC50HT5DK4LqQ4zeSSrE/ffT qpnPQ9MofxHdmmGJ+4t26xxl58cBEDTgMLWUxPxUOc7Ofn1b+pJ6qvurbfFYmKAim6C1 s/ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=5uXpXBV+OrlAdQTmFu5ZT22P0Vb23q/Dhu3v7reLSeg=; b=feSKFgYtwGNRdC4eH3ulGtZyIhFFeDTHrXpw1ode0Joo00aR2qHSoL7oUJKbLeAuvX MIwhon8dK6hHDav5A7yBwHg3G0IK0R4yIkh8XMAj/CyT2tgi+DBqbTqOOGwrmvRGXSwU w5OyjKu2MDNtsdaZ+SAzqcrAUmH3nO0qVj13mYQwmkWxX/a+ubTz8b7RSkHv9GUoO3yf DOayLSobkHPoXeOYfwiTzPKEz9y3426nSFPHYzZRhS6c4myO0QNzKatj3MsfIHeLXsig XoJ9WRMEc9vIkRnvbJnZ/xGjbc787odGRFpSYWrQ+sV79aAbdba/CMGZI4b1v4z3zo4k xn1A== X-Gm-Message-State: AJcUukceZgJ7b+Juvz4G6+NSgFUlWSb00VhN+UDC2zSGaVgAqjCbC6iL fT9SxjsvQg/iHn6h01mWbi+m+A== X-Google-Smtp-Source: ALg8bN56F1BARMRxjQN0TQJ3+s1QLZsV1DItltBuIFc5POHRYAH8y3l1/uh3na1tqu9qOWNBl1OgeQ== X-Received: by 2002:a63:8b41:: with SMTP id j62mr13199080pge.182.1547723048777; Thu, 17 Jan 2019 03:04:08 -0800 (PST) Received: from localhost.localdomain ([106.51.16.164]) by smtp.gmail.com with ESMTPSA id h15sm1688142pgl.43.2019.01.17.03.04.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Jan 2019 03:04:08 -0800 (PST) From: Anup Patel <anup@brainfault.org> To: Rick Chen <rick@andestech.com>, Bin Meng <bmeng.cn@gmail.com>, Joe Hershberger <joe.hershberger@ni.com>, Lukas Auer <lukas.auer@aisec.fraunhofer.de>, Masahiro Yamada <yamada.masahiro@socionext.com>, Simon Glass <sjg@chromium.org> Date: Thu, 17 Jan 2019 16:33:45 +0530 Message-Id: <20190117110356.36753-1-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 Cc: Palmer Dabbelt <palmer@sifive.com>, U-Boot Mailing List <u-boot@lists.denx.de>, Alexander Graf <agraf@suse.de>, Christoph Hellwig <hch@infradead.org>, Paul Walmsley <paul.walmsley@sifive.com> Subject: [U-Boot] [PATCH 00/11] SiFive FU540 Support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <http://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> |
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SiFive FU540 Support
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Hi All, My apologies for spaming some of you. First time I send patches using anup.patel@wdc.com which got block U-Boot mailing list server (Don't know why). Regards, Anup
From: Anup Patel <anup.patel@wdc.com> This patchset adds SiFive Freedom Unleashed (FU540) support to RISC-V U-Boot. The patches are based upon latest RISC-V U-Boot tree (git://git.denx.de/u-boot-riscv.git) at commit id 91882c472d8c0aef4db699d3f2de55bf43d4ae4b All drivers namely: SiFive PRCI, SiFive Serial, and Cadance MACB Ethernet work fine on actual SiFive Unleashed board and QEMU sifive_u machine. Anup Patel (7): riscv: Rename cpu/qemu to cpu/generic riscv: Add asm/dma-mapping.h for DMA mappings riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems net: macb: Fix clk API usage for RISC-V systems clk: Add SiFive FU540 PRCI clock driver clk: Add fixed-factor clock driver riscv: Add SiFive FU540 board support Atish Patra (4): net: macb: Fix GEM hardware detection drivers: serial_sifive: Fix baud rate calculation drivers: serial: serial_sifive: Skip baudrate config if no input clock cpu: Bind timer driver for boot hart arch/riscv/Kconfig | 6 +- arch/riscv/cpu/{qemu => generic}/Kconfig | 2 +- arch/riscv/cpu/{qemu => generic}/Makefile | 0 arch/riscv/cpu/{qemu => generic}/cpu.c | 0 arch/riscv/cpu/generic/dram.c | 39 ++ arch/riscv/cpu/qemu/dram.c | 17 - arch/riscv/include/asm/dma-mapping.h | 38 ++ board/emulation/qemu-riscv/Kconfig | 4 +- .../qemu-riscv => sifive/fu540}/Kconfig | 36 +- board/sifive/fu540/MAINTAINERS | 9 + board/sifive/fu540/Makefile | 5 + board/sifive/fu540/fu540.c | 17 + configs/sifive_fu540_defconfig | 11 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 5 +- drivers/clk/clk_fixed_factor.c | 74 +++ drivers/clk/sifive/Kconfig | 19 + drivers/clk/sifive/Makefile | 5 + .../clk/sifive/analogbits-wrpll-cln28hpc.h | 101 +++ drivers/clk/sifive/fu540-prci.c | 604 ++++++++++++++++++ drivers/clk/sifive/wrpll-cln28hpc.c | 390 +++++++++++ drivers/cpu/riscv_cpu.c | 7 +- drivers/net/macb.c | 6 +- drivers/serial/serial_sifive.c | 60 +- include/configs/sifive-fu540.h | 43 ++ include/dt-bindings/clk/sifive-fu540-prci.h | 29 + 26 files changed, 1467 insertions(+), 61 deletions(-) rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%) rename arch/riscv/cpu/{qemu => generic}/Makefile (100%) rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%) create mode 100644 arch/riscv/cpu/generic/dram.c delete mode 100644 arch/riscv/cpu/qemu/dram.c create mode 100644 arch/riscv/include/asm/dma-mapping.h copy board/{emulation/qemu-riscv => sifive/fu540}/Kconfig (57%) create mode 100644 board/sifive/fu540/MAINTAINERS create mode 100644 board/sifive/fu540/Makefile create mode 100644 board/sifive/fu540/fu540.c create mode 100644 configs/sifive_fu540_defconfig create mode 100644 drivers/clk/clk_fixed_factor.c create mode 100644 drivers/clk/sifive/Kconfig create mode 100644 drivers/clk/sifive/Makefile create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h create mode 100644 drivers/clk/sifive/fu540-prci.c create mode 100644 drivers/clk/sifive/wrpll-cln28hpc.c create mode 100644 include/configs/sifive-fu540.h create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h