From patchwork Tue Oct 30 12:55:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 991346 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42lR0v6PXqz9s1c for ; Wed, 31 Oct 2018 22:28:31 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 82743C2224B; Wed, 31 Oct 2018 11:28:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D64C5C2225B; Wed, 31 Oct 2018 11:26:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EA0DDC220E1; Tue, 30 Oct 2018 12:57:09 +0000 (UTC) Received: from mail-edgeKA24.fraunhofer.de (mail-edgeka24.fraunhofer.de [153.96.1.24]) by lists.denx.de (Postfix) with ESMTPS id 888EBC220DC for ; Tue, 30 Oct 2018 12:57:09 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2GEAAC/VNhb/xoBYJlkHAEBAQQBAQcEAQGBUgYBAQsBggRmgSeHQIUtm22IeRSBKzsNIwuBAoM8gyciNQwNAQMBAQIBAQICAmkcDIJmBEs7LwEBAQEBAQEBAQEBAQEBAQEaAg0mgTgFLX0UDoMmAYIAAQ+qHoNxPAGFeAkBhzeEJoFYP4EQAYYtAoFJhXMCiFkkgWqUKQcCgQ6BBASEVYoRCxiBUkyHHIcOiTmDPYZ0AYM7gUUBNoFVMxokT4JsCYJGgzaEH4Y0bot4AQE X-IPAS-Result: A2GEAAC/VNhb/xoBYJlkHAEBAQQBAQcEAQGBUgYBAQsBggRmgSeHQIUtm22IeRSBKzsNIwuBAoM8gyciNQwNAQMBAQIBAQICAmkcDIJmBEs7LwEBAQEBAQEBAQEBAQEBAQEaAg0mgTgFLX0UDoMmAYIAAQ+qHoNxPAGFeAkBhzeEJoFYP4EQAYYtAoFJhXMCiFkkgWqUKQcCgQ6BBASEVYoRCxiBUkyHHIcOiTmDPYZ0AYM7gUUBNoFVMxokT4JsCYJGgzaEH4Y0bot4AQE X-IronPort-AV: E=Sophos;i="5.54,444,1534802400"; d="scan'208";a="10904625" Received: from mail-mtaka26.fraunhofer.de ([153.96.1.26]) by mail-edgeKA24.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2018 13:57:08 +0100 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0BSAACMVNhb/xBhWMBkHQEBBQEHBQGBUgcBCwGCam06jG2bbYh5FIFmDSOESYNINQwNAQMBAQIBAQJtHAyGNQUtfRQOgyYBggEPqh+ELQGFeAkBhzeFfj+BEAGGLQKBSYVzAohZJIFqlCkHAoEOgQQEhFWKEQsYgVJMhxyHDok5gz2KMIFFATWBVTMaJE+CbAmCRoM2hB+GND4wi3gBAQ X-IronPort-AV: E=Sophos;i="5.54,444,1534802400"; d="scan'208";a="16525629" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP12EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA26.fraunhofer.de with ESMTP/TLS/AES256-SHA; 30 Oct 2018 13:57:07 +0100 Received: from muc-nb-035.aisec.fraunhofer.de (10.80.233.51) by FGDEMUCIMP12EXC.ads.fraunhofer.de (10.80.232.43) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 30 Oct 2018 13:57:06 +0100 From: Lukas Auer To: Date: Tue, 30 Oct 2018 13:55:23 +0100 Message-ID: <20181030125553.5230-1-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.17.2 MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24188.007 X-TM-AS-Result: No--5.440500-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-Mailman-Approved-At: Wed, 31 Oct 2018 11:26:43 +0000 Cc: Michal Simek , Marek Vasut , Stephen Warren , Heinrich Schuchardt , Alexander Graf , Macpaul Lin , Greentime Hu , Rajan Vaja Subject: [U-Boot] [PATCH v2 00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch series includes general fixes and cleanup for RISC-V. It also adds support for booting Linux on qemu-riscv. At the moment, only single-core systems are supported. Support for multi-core systems will be added with a future patch series. To boot Linux on qemu-riscv, Linux must be compiled into BBL as a payload. BBL must be included in a FIT image and supplied to QEMU with the -kernel parameter. Its location in memory is embedded in the device tree, which QEMU passes to u-boot. To test this, QEMU and riscv-pk (BBL) must be modified. QEMU is modified to add support for loading binary files (FIT images in this case) in addition to ELF files. riscv-pk must be modified to adjust the link address. A pull request for QEMU, which implements this, is available at [1]. A modified version of riscv-pk is available at [2]. This series applies on top of u-boot-dm/next. [1]: https://github.com/riscv/riscv-qemu/pull/175 [2]: https://github.com/lukasauer/riscv-pk/tree/riscv-u-boot Changes in v2: - Replace the description of RISCV_ISA_C with that of the Linux kernel, as suggested by Bin Meng - Change ISA string construction, as suggested by Bin Meng - Change ISA string construction, as suggested by Bin Meng - Remove 0-padding in the format string to avoid printing 16 digits on RV32I systems - Clarify reasoning behind patch in commit message - New patch to replace patch "riscv: remove CONFIG_INIT_CRITICAL" - Drop removal of code that stores the contents of a2; this broke the board ax25-ae350. The code will be removed again in a future patch. - Rebase onto u-boot-dm/next - New patch - Rebase onto u-boot-dm/next - Move prototype location to match the location of the function in ofnode.c - Rebase onto u-boot-dm/next - Boot Linux with the device tree provided by the prior boot stage - New patch Bin Meng (1): Drop CONFIG_INIT_CRITICAL Lukas Auer (28): tools: .gitignore: add prelink-riscv dts: riscv: update makefile to also clean the RISC-V dts directory riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I riscv: select CONFIG_PHYS_64BIT on RV64I systems riscv: add Kconfig entries for the C and A ISA extensions riscv: set -march and -mabi based on the Kconfig configuration riscv: add Kconfig entries for the code model riscv: enable -fdata-sections riscv: fix use of incorrectly sized variables riscv: make use of the barrier functions from Linux riscv: do not reimplement generic io functions riscv: complete the list of exception codes riscv: treat undefined exception codes as reserved riscv: hang on unhandled exceptions riscv: implement the invalidate_icache_* functions riscv: invalidate the instruction cache before jumping to Linux riscv: fix inconsistent use of spaces and tabs in start.S riscv: align mtvec on a 4-byte boundary riscv: remove unused labels in start.S riscv: do not blindly modify the mstatus CSR riscv: save hart ID and device tree passed by prior boot stage riscv: qemu: use device tree passed by prior boot stage riscv: store device tree passed by prior boot stage in environment riscv: qemu: support booting Linux riscv: align bootm implementation with that of other architectures dm: core: add missing prototype for ofnode_read_u64 riscv: qemu: detect and boot the kernel passed by QEMU riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL arch/Kconfig | 1 + arch/nds32/cpu/n1213/start.S | 51 ---- arch/riscv/Kconfig | 47 +++- arch/riscv/Makefile | 27 ++ arch/riscv/config.mk | 7 +- arch/riscv/cpu/cpu.c | 13 + arch/riscv/cpu/start.S | 342 ++++++++++++------------ arch/riscv/include/asm/barrier.h | 67 +++++ arch/riscv/include/asm/io.h | 48 +--- arch/riscv/include/asm/posix_types.h | 6 +- arch/riscv/include/asm/types.h | 4 + arch/riscv/include/asm/u-boot-riscv.h | 1 + arch/riscv/lib/bootm.c | 98 +++++-- arch/riscv/lib/cache.c | 10 + arch/riscv/lib/interrupts.c | 31 ++- arch/riscv/lib/setjmp.S | 2 +- board/armltd/integrator/README | 4 +- board/emulation/qemu-riscv/Kconfig | 2 + board/emulation/qemu-riscv/qemu-riscv.c | 73 ++++- configs/ax25-ae350_defconfig | 2 +- configs/qemu-riscv32_defconfig | 4 +- configs/qemu-riscv64_defconfig | 6 +- dts/Makefile | 2 +- include/common.h | 5 - include/config_distro_bootcmd.h | 8 +- include/configs/qemu-riscv.h | 14 + include/dm/ofnode.h | 10 + scripts/config_whitelist.txt | 1 - tools/.gitignore | 1 + 29 files changed, 543 insertions(+), 344 deletions(-) create mode 100644 arch/riscv/include/asm/barrier.h