From patchwork Fri Oct 19 22:07:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 987056 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42cKmv6g7Cz9sjG for ; Sat, 20 Oct 2018 09:08:28 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id CCF19C21DED; Fri, 19 Oct 2018 22:08:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 38488C21C27; Fri, 19 Oct 2018 22:08:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3A327C21C27; Fri, 19 Oct 2018 22:08:17 +0000 (UTC) Received: from mail-edgeDD24.fraunhofer.de (mail-edgeDD24.fraunhofer.de [192.102.167.24]) by lists.denx.de (Postfix) with ESMTPS id C26BCC21BE5 for ; Fri, 19 Oct 2018 22:08:16 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2FpAgCcVcpb/xwBYJlkGwEBAQEDAQEBBwMBAQGBZYIFZm06hz+FLYs7gweNIIo0Ow0jC4ECgzyFCyE4FgEDAQECAQECAgJpHAyCZgRLOy8BAQEBAQEBAQEBAQEBAQEBGgINJoE4BS1xDBQOgyYBggABD6hwg3E7AYVtCQGHIoQjgVg/gRABgl2DUAKHOwKIbZVUBwKBDYEBBIRMigMLF4FPTIcQhn6JI4MxhkkBgzSBWiKBVTMaJE+CbAmFfIQfhjVtjCUBAQ X-IPAS-Result: A2FpAgCcVcpb/xwBYJlkGwEBAQEDAQEBBwMBAQGBZYIFZm06hz+FLYs7gweNIIo0Ow0jC4ECgzyFCyE4FgEDAQECAQECAgJpHAyCZgRLOy8BAQEBAQEBAQEBAQEBAQEBGgINJoE4BS1xDBQOgyYBggABD6hwg3E7AYVtCQGHIoQjgVg/gRABgl2DUAKHOwKIbZVUBwKBDYEBBIRMigMLF4FPTIcQhn6JI4MxhkkBgzSBWiKBVTMaJE+CbAmFfIQfhjVtjCUBAQ X-IronPort-AV: E=Sophos;i="5.54,401,1534802400"; d="scan'208";a="7272561" Received: from mail-mtaka28.fraunhofer.de ([153.96.1.28]) by mail-edgeDD24.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Oct 2018 00:08:06 +0200 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0DkAwAiVcpb/xBhWMBkHQEBBQEHBQGBZYJrgSeMbI5CjSCKbw0jhEmFKzgWAQMBAQIBAQJtHAyGNQUtcQwUDoMmAYIBD6hwhCwBhW0JAYcihXs/gRABgl2DUAKHOwKIbZVUBwKBDYEBBIRMigMLF4FPTIcQhn6JI4MxiX6BWiGBVTMaJE+CbAmFfIQfhjU9MIwlAQE X-IronPort-AV: E=Sophos;i="5.54,401,1534802400"; d="scan'208";a="18910081" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP11EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA28.fraunhofer.de with ESMTP/TLS/AES256-SHA; 20 Oct 2018 00:08:05 +0200 Received: from localhost.de (10.80.233.50) by FGDEMUCIMP11EXC.ads.fraunhofer.de (10.80.232.42) with Microsoft SMTP Server (TLS) id 14.3.408.0; Sat, 20 Oct 2018 00:09:23 +0200 From: Lukas Auer To: Date: Sat, 20 Oct 2018 00:07:13 +0200 Message-ID: <20181019220743.15020-1-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.17.2 MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24166.002 X-TM-AS-Result: No--6.488100-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Heinrich Schuchardt , Alexander Graf , Greentime Hu Subject: [U-Boot] [PATCH 00/30] General fixes / cleanup for RISC-V and improvements to qemu-riscv X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch series includes general fixes and cleanup for RISC-V. It also adds support for booting Linux on qemu-riscv. At the moment, only single-core systems are supported. Support for multi-core systems will be added with a future patch series. To boot Linux on qemu-riscv, Linux must be compiled into BBL as a payload. BBL must be included in a FIT image and supplied to QEMU with the -kernel parameter. Its location in memory is embedded in the device tree, which QEMU passes to u-boot. To test this, QEMU and riscv-pk (BBL) must be modified. QEMU is modified to add support for loading binary files (FIT images in this case) in addition to ELF files. riscv-pk must be modified to adjust the link address and to ignore the kernel address from the device tree. A pull request for QEMU, which implements this, is available at [1]. A modified version of riscv-pk is available at [2]. [1]: https://github.com/riscv/riscv-qemu/pull/175 [2]: https://github.com/lukasauer/riscv-pk/tree/riscv-u-boot Lukas Auer (30): tools: .gitignore: add prelink-riscv riscv: ignore device tree binaries dts: riscv: update makefile to also clean the RISC-V dts directory riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I riscv: select CONFIG_PHYS_64BIT on RV64I systems riscv: add Kconfig entries for the C and A ISA extensions riscv: set -march and -mabi based on the Kconfig configuration riscv: add Kconfig entries for the code model riscv: move target selection into separate file riscv: enable -fdata-sections riscv: fix use of incorrectly sized variables riscv: make use of the barrier functions from Linux riscv: do not reimplement generic io functions riscv: complete the list of exception codes riscv: treat undefined exception codes as reserved riscv: hang on unhandled exceptions riscv: implement the invalidate_icache_* functions riscv: invalidate the instruction cache before jumping to Linux riscv: fix inconsistent use of spaces and tabs in start.S riscv: align mtvec on a 4-byte boundary riscv: remove CONFIG_INIT_CRITICAL riscv: remove unused labels in start.S riscv: do not blindly modify the mstatus CSR riscv: save hart ID and device tree passed by prior boot stage riscv: qemu: use device tree passed by prior boot stage bdinfo: riscv: print fdt_blob address riscv: qemu: support booting Linux riscv: align bootm implementation with that of other architectures dm: core: add missing prototype for ofnode_read_u64 riscv: qemu: detect and boot the kernel passed by QEMU arch/riscv/Kconfig | 54 ++-- arch/riscv/Kconfig.board | 14 + arch/riscv/Makefile | 16 ++ arch/riscv/config.mk | 7 +- arch/riscv/cpu/cpu.c | 6 + arch/riscv/cpu/start.S | 339 +++++++++++------------- arch/riscv/dts/.gitignore | 1 + arch/riscv/include/asm/barrier.h | 67 +++++ arch/riscv/include/asm/io.h | 48 +--- arch/riscv/include/asm/posix_types.h | 6 +- arch/riscv/include/asm/types.h | 4 + arch/riscv/lib/bootm.c | 93 +++++-- arch/riscv/lib/cache.c | 10 + arch/riscv/lib/interrupts.c | 31 ++- arch/riscv/lib/setjmp.S | 2 +- board/emulation/qemu-riscv/Kconfig | 1 + board/emulation/qemu-riscv/qemu-riscv.c | 35 ++- cmd/bdinfo.c | 2 + configs/ax25-ae350_defconfig | 2 +- configs/qemu-riscv32_defconfig | 4 +- configs/qemu-riscv64_defconfig | 6 +- dts/Makefile | 2 +- include/config_distro_bootcmd.h | 8 +- include/configs/qemu-riscv.h | 13 + include/dm/ofnode.h | 10 + tools/.gitignore | 1 + 26 files changed, 494 insertions(+), 288 deletions(-) create mode 100644 arch/riscv/Kconfig.board create mode 100644 arch/riscv/dts/.gitignore create mode 100644 arch/riscv/include/asm/barrier.h