From patchwork Mon Jun 11 08:08:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carlo Caione X-Patchwork-Id: 927520 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=caione.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="lVlEine3"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4145Hm0H8bz9s2t for ; Mon, 11 Jun 2018 18:08:34 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E58C0C21DF9; Mon, 11 Jun 2018 08:08:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3EA61C21C51; Mon, 11 Jun 2018 08:08:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BECABC21C50; Mon, 11 Jun 2018 08:08:23 +0000 (UTC) Received: from mail-wm0-f52.google.com (mail-wm0-f52.google.com [74.125.82.52]) by lists.denx.de (Postfix) with ESMTPS id D611AC21BE5 for ; Mon, 11 Jun 2018 08:08:21 +0000 (UTC) Received: by mail-wm0-f52.google.com with SMTP id r125-v6so14550016wmg.2 for ; Mon, 11 Jun 2018 01:08:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=UxbamuewTATcK4pqNkayUrfKybD8fNreYjXJMnFSmFc=; b=lVlEine3RPQyFDxTXYYSG2m9Ee+eewV1ThMCmGFzoiHw8tGMJpM1GBR/wPz+tSOIr/ jCB/cDLBMWLCF3kIBNY4n2Xgg3KKglsWrh1Oxlr9rOL93LpPqqswlstNwKPd5MbHhwwq iCEXbugsnmJiFRDhRlFTC7v4xHobb7yJ3wuV+uUATpy/Zg49E15RYUey45K6tBs1Nu5c L1lJuVq64IgFKk3G+30//EABA2PjQvVmk4ZTDeixWKlJ+5qkJ3PIUX1PBy/m3SS+yXwz Ir6Ifb2vpMfdnK8l6JMwpU4Gz/Xm1CC0WVx0H10g2Q4DFDsLixHETMjRo/JKObMc+MdI OISw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=UxbamuewTATcK4pqNkayUrfKybD8fNreYjXJMnFSmFc=; b=qvrtcEpoeW/oQKi8zTAkYVl5L/WOHQPVmmjpkHxIo1HlzfMphdUot8bsOBO4ZqidFD fLlSZaDdzbwF6Biji52NIglR8XPCrHCP+ST2mgFX8cAoJsdkwwkauXXxZh0JFAL8wQKu XeA03pKshDY5kRUZpcigSsPrITAbpBummsV6MVLCAOSUJ1wWKHa2QeFIvHjsUOTd8JRO uv8APhLA3SEmBwnDLHiXg+bBoNDpTSAkxcQPi5xXtOU9RdQFeDspbC7U61eX7t0jsNsX hAprcKyTNou8PRZMDI6P0fxCP6TFfevTLJj6GPipshKhqTinIT89Hh6yW9yslM0BTGR9 USlw== X-Gm-Message-State: APt69E25dkGUKVTFxvdneWkqyofLHnrRIyG1nk3lvr4so0BXg3Pb+0cI pnXkFmNhumhwWHQNr4A4Fvs= X-Google-Smtp-Source: ADUXVKKNi3t2/hz+bO5WgJ+Q6FGCR1MqNkUW6OapkVM1Lv75c/Vk10qUcu8fAgtMP9d0soIIwGamJQ== X-Received: by 2002:a1c:4291:: with SMTP id k17-v6mr7009580wmi.74.1528704501433; Mon, 11 Jun 2018 01:08:21 -0700 (PDT) Received: from localhost.localdomain ([185.49.42.196]) by smtp.gmail.com with ESMTPSA id j13-v6sm63336802wre.38.2018.06.11.01.08.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Jun 2018 01:08:20 -0700 (PDT) From: Carlo Caione To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com, albert.u.boot@aribaud.net, u-boot@lists.denx.de, linux@endlessm.com Date: Mon, 11 Jun 2018 09:08:09 +0100 Message-Id: <20180611080812.16786-1-carlo@caione.org> X-Mailer: git-send-email 2.17.1 Cc: Carlo Caione Subject: [U-Boot] [PATCH v2 0/3] rk3288: veyron: Enable SDMMC when booting from SPI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Carlo Caione These patches toghether with the previously submitted patch [0] enable the chromebook veyron jerry to use the SDMMC interface when U-Boot is not chainloaded by depthcharge but booted directly from SPI. [0] https://marc.info/?l=u-boot&m=152836928803742&w=2 Changelog: V2: - Add Reviewed-by - Expand comment on PATCH 2/3 Carlo Caione (3): rk3288: veyron: Init boot-on regulators rk3288: Disable JTAG function from sdmmc0 IO rockchip: veyron: Set vcc33_sd regulator value arch/arm/mach-rockchip/rk3288-board.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)