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Fri, 10 Jul 2020 08:38:40 +0000 From: Sagar Shrikant Kadam To: u-boot@lists.denx.de Cc: rick@andestech.com, paul.walmsley@sifive.com, palmer@dabbelt.com, anup.patel@wdc.com, atish.patra@wdc.com, lukma@denx.de, pragnesh.patel@sifive.com, bin.meng@windriver.com, jagan@amarulasolutions.com, sjg@chromium.org, twoerner@gmail.com, abrodkin@synopsys.com, Eugeniy.Paltsev@synopsys.com, patrick@blueri.se, weijie.gao@mediatek.com, festevam@gmail.com, Sagar Shrikant Kadam Subject: [PATCH v3 0/5] add DM based reset driver for SiFive SoC's Date: Fri, 10 Jul 2020 01:38:23 -0700 Message-Id: <1594370308-30957-1-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 X-ClientProxiedBy: BYAPR04CA0011.namprd04.prod.outlook.com (2603:10b6:a03:40::24) To BN8PR13MB2611.namprd13.prod.outlook.com (2603:10b6:408:81::17) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from gamma07.internal.sifive.com (64.62.193.194) by BYAPR04CA0011.namprd04.prod.outlook.com (2603:10b6:a03:40::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3174.20 via Frontend Transport; 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SFTY:; SFS:(6029001)(136003)(346002)(396003)(366004)(376002)(39850400004)(186003)(26005)(6666004)(4743002)(83380400001)(66556008)(8936002)(66476007)(956004)(8676002)(6486002)(107886003)(2906002)(4326008)(7416002)(86362001)(7696005)(52116002)(2616005)(478600001)(36756003)(66946007)(316002)(5660300002)(16526019)(6916009); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: mvCR3sajN5LewtGEAQbQ9EtJiHDLDDPBKsgovwVAofSde2bsdlyMFPtMR7Y1ME3j/BdwrUgAz3cZ06MqmqpQWkJJHXtXdGv/qMgGqkek5z20oxQI/mjOdXec6Z8Nu2+s0Kl21bDlhKdXRLvWD+4SvBOAk3GNUTbAU4Bd+2uYNsDLd5gLtKzY3dIv8cJq7VYER8pcwxeiUD7DaCftLac1WYYjrpZENkCRuLAS3SQxw3MiePMESIPWAkxMxIleLMM8ZM6kCDnZfBk8fI9X0g7QB0yXEcqnMg8ujlau3oSbYTaF5wxat8wTSoaorhCfm+++kGmDc24T4whbncZSeHKVfnTJT4paXEPZHRYaHS7IPoLWnqgDgwN5vQAzRed2xwS6FAdXdkEO+4aO7ogXpjMQOWpiDibPJg2ssHleV7kOxZUVi0QTUsPfMG1nymv0IrGK9OfhZ9Vo8yA1ahnveXepUydQIGsRN43SoOm/zf+gsyHZr4Gb0iwJI3oem0/esv10 X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: 19ad1f33-e1c5-41f5-bbb3-08d824aca56b X-MS-Exchange-CrossTenant-AuthSource: BN8PR13MB2611.namprd13.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2020 08:38:40.2890 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9DCMd01BNfpGGrLZ4uCVYyxFTuHgW/7n3cbsa2gxtyiLSaniwBWyk2xVthgfKAiXyrtF/1XbsCz3sdgR0OqJGw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR13MB1698 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean The FU540-C000 support in U-Boot is missing DM based reset driver, and is handling reset's to sub-system within the prci driver itself. The series here adds a generic DM reset driver for SiFive SoC's so as to leverage the U-Boot's reset framework and binds the reset driver with prci driver. The PRCI driver takes care of triggering the consumers reset signals appropriately. Patch 1: Add necessary dt indexes for device reset register. Patch 2: Update macro's to use common dt indexes from binding header. Patch 3: Add reset producer and consumer entries within the device tree. Patch 4: Add reset dm driver and bind it within prci module. Patch 5: Add Kconfig, Makefile entries and enable the driver This series is based on mainline U-Boot commit 2f5fbb5b39f7 ("Prepare v2020.07") History: ========================== V3: -Add reset indexes in separate dt binding header instead of updating the clock dt binding header which is synced from Linux V2: -Removed extra character in commit log of 2nd patch V1: -Base version. Sagar Shrikant Kadam (5): dt-bindings: prci: add indexes for reset signals available in prci fu540: prci: use common reset indexes defined in binding header fu540: dtsi: add reset producer and consumer entries sifive: reset: add DM based reset driver for SiFive SoC's configs: reset: fu540: enable dm reset framework for SiFive SoC arch/riscv/dts/fu540-c000-u-boot.dtsi | 12 +++ arch/riscv/include/asm/arch-fu540/reset.h | 13 +++ configs/sifive_fu540_defconfig | 2 + drivers/clk/sifive/fu540-prci.c | 90 ++++++++++++++------ drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-sifive.c | 118 ++++++++++++++++++++++++++ include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++ 8 files changed, 239 insertions(+), 25 deletions(-) create mode 100644 arch/riscv/include/asm/arch-fu540/reset.h create mode 100644 drivers/reset/reset-sifive.c create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h