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Sun, 28 Jun 2020 14:45:12 +0000 From: Sagar Shrikant Kadam To: u-boot@lists.denx.de Cc: rick@andestech.com, bin.meng@windriver.com, jagan@amarulasolutions.com, pragnesh.patel@sifive.com, anup.patel@wdc.com, sjg@chromium.org, ye.li@nxp.com, peng.fan@nxp.com, seanga2@gmail.com, Sagar Shrikant Kadam Subject: [PATCH v7 0/4] update clock handler and proper cpu features Date: Sun, 28 Jun 2020 07:44:59 -0700 Message-Id: <1593355503-24938-1-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 X-ClientProxiedBy: BY5PR17CA0001.namprd17.prod.outlook.com (2603:10b6:a03:1b8::14) To BN8PR13MB2611.namprd13.prod.outlook.com (2603:10b6:408:81::17) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from gamma07.internal.sifive.com (64.62.193.194) by BY5PR17CA0001.namprd17.prod.outlook.com (2603:10b6:a03:1b8::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3131.20 via Frontend Transport; Sun, 28 Jun 2020 14:45:11 +0000 X-Mailer: git-send-email 2.7.4 X-Originating-IP: [64.62.193.194] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c7c049d1-9ac5-463b-6f73-08d81b71dcd5 X-MS-TrafficTypeDiagnostic: BN8PR13MB2689: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:400; 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The current "cpu detail" sometimes shows "Microcode" as a feature, which is not the case with FU540-C000 on HiFive Unleashed board. Patch 1: add cpu node aliases. Patch 2: Init CPU information to avoid inconsistent cpu information. Patch 3: Correctly parse and update mmu-type. Patch 4: Set L1 Cache feature if either i-cache or d-cache is present I have picked few dependent patches from Sean's series from here [1] and [2]. These have applied on mainline U-Boot commit eae62ae8de18 ("Merge tag 'efi-2020-07-rc6' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi") Patch history: ============================================= v7: -Included the nits suggestion. V6: -Rebase series with master -Split patch 2 from v5 as suggested i.e init cpu feature in cpu-class.c as one patch and handle mmu-type check into another. -Updated Reviewed-by tags V5: -Addressed review comments on v4. 1. Removed patch 1 which was for debug message. 2. Updated commit logs with proper information on number of cpu's 3. Additionally used d-cache to set the L1 feature bit. V4: 1. Rebased the series to mainline commit. 2. Updated dependency list as few patches are now merged. 3. Added U-Boot log of the flow i.e fsbl + fw_payload.bin (Opensbi+U-Boot) V3: 1. Included the cosmetic change as suggested s/L1 feature/L1 cache feature/ 2. Added Reviewed-By tags V2: 1. Incorporate review comments from Bin and Sean Anderson. and dropped 2nd patch as similar work was already done in [1] and [2] 2 Add cpu node aliases to display cpu node's in sequence. 3. Add fix to show mmu as available cpu feature. 4. Check and append L1 cache feature. V1: Base version Thanks to Vincent Chen for testing the V1 version of this series. [1] https://patchwork.ozlabs.org/patch/1316066 [2] https://patchwork.ozlabs.org/patch/1316067 All these together is available here: https://github.com/sagsifive/u-boot/commits/dev/sagark/clk-v7 U-Boot log: =========================================================== U-Boot SPL 2020.07-rc5-00063-g213d48a (Jun 28 2020 - 07:19:43 -0700) Trying to boot from MMC1 U-Boot 2020.07-rc5-00063-g213d48a (Jun 28 2020 - 07:19:43 -0700) CPU: rv64imafdc Model: SiFive HiFive Unleashed A00 DRAM: 8 GiB MMC: spi@10050000:mmc@0: 0 In: serial@10010000 Out: serial@10010000 Err: serial@10010000 Net: eth0: ethernet@10090000 Hit any key to stop autoboot: 0 => => cpu list 1: cpu@1 rv64imafdc 2: cpu@2 rv64imafdc 3: cpu@3 rv64imafdc 4: cpu@4 rv64imafdc => cpu detail 1: cpu@1 rv64imafdc ID = 1, freq = 999.100 MHz: L1 cache, MMU 2: cpu@2 rv64imafdc ID = 2, freq = 999.100 MHz: L1 cache, MMU 3: cpu@3 rv64imafdc ID = 3, freq = 999.100 MHz: L1 cache, MMU 4: cpu@4 rv64imafdc ID = 4, freq = 999.100 MHz: L1 cache, MMU => Sagar Shrikant Kadam (4): riscv: dts: hifive-unleashed-a00: add cpu aliases uclass: cpu: fix to display proper CPU features riscv: cpu: correctly handle the setting of CPU_FEAT_MMU bit riscv: cpu: check and append L1 cache to cpu features arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4 ++++ drivers/cpu/cpu-uclass.c | 3 +++ drivers/cpu/riscv_cpu.c | 17 +++++++++++++---- 3 files changed, 20 insertions(+), 4 deletions(-)