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Thu, 4 Jun 2020 10:44:50 +0000 From: Sagar Shrikant Kadam To: u-boot@lists.denx.de, rick@andestech.com, lukma@denx.de Cc: bmeng.cn@gmail.com, jagan@amarulasolutions.com, pragnesh.patel@sifive.com, anup.patel@wdc.com, sjg@chromium.org, seanga2@gmail.com, Sagar Shrikant Kadam Subject: [PATCH v3 0/4] update clock handler and proper cpu features Date: Thu, 4 Jun 2020 03:44:35 -0700 Message-Id: <1591267479-8900-1-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 X-ClientProxiedBy: BYAPR06CA0042.namprd06.prod.outlook.com (2603:10b6:a03:14b::19) To BN8PR13MB2611.namprd13.prod.outlook.com (2603:10b6:408:81::17) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from gamma07.internal.sifive.com (64.62.193.194) by BYAPR06CA0042.namprd06.prod.outlook.com (2603:10b6:a03:14b::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3066.18 via Frontend Transport; Thu, 4 Jun 2020 10:44:48 +0000 X-Mailer: git-send-email 2.7.4 X-Originating-IP: [64.62.193.194] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 75b2f731-a75f-43c8-0fd2-08d808744e63 X-MS-TrafficTypeDiagnostic: BN6PR13MB1076: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:475; 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The current "cpu detail" sometimes shows "Microcode" as a feature, which is not the case with FU540-C000 on HiFive Unleashed board. Patch 1: add clk request handler to check if valid clock id is requested. Patch 2: add cpu node aliases. Patch 3: Correctly parse and update mmu-type. RISC-V core's on FU540-C000 SoC have separate instruction and data (split) L1 cache. Patch 4:Use i-cache-size dt property as one of identifier to indicate a split cache is available. I have picked few dependent patches from Sean's and Pragnesh's latest series from here [1]...[5]. These have applied on mainline U-Boot commit 0d8f35b58cc8 ("Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi") Patch history: ============================================= V3: 1. Included the cosmetic change as suggested s/L1 feature/L1 cache feature/ 2. Added Reviewed-By tags V2: 1. Incorporate review comments from Bin and Sean Anderson. and dropped 2nd patch as similar work was already done in [1] and [2] 2 Add cpu node aliases to display cpu node's in sequence. 3. Add fix to show mmu as available cpu feature. 4. Check and append L1 cache feature. V1: Base version Thanks to Vincent Chen for testing the V1 version of this series. [1] https://patchwork.ozlabs.org/patch/1295345 [2] https://patchwork.ozlabs.org/patch/1295346 [3] https://patchwork.ozlabs.org/patch/1300369 [4] https://patchwork.ozlabs.org/patch/1300370 [5] https://patchwork.ozlabs.org/patch/1300373 All these together is available here: https://github.com/sagsifive/u-boot/commits/dev/sagark/clk-v3 Sagar Shrikant Kadam (4): fu540: prci: add request and free clock handlers riscv: dts: hifive-unleashed-a00: add cpu aliases riscv: cpu: fixes to display proper CPU features riscv: cpu: check and append L1 cache to cpu features arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 5 +++++ drivers/clk/sifive/fu540-prci.c | 21 +++++++++++++++++++++ drivers/cpu/riscv_cpu.c | 10 +++++++++- 3 files changed, 35 insertions(+), 1 deletion(-)