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Tue, 28 Jan 2020 18:02:21 +0000 From: Sagar Shrikant Kadam To: u-boot@lists.denx.de Subject: [U-Boot Patch v2 0/4] Fix currently available support for flash on HiFive Unleashed Date: Tue, 28 Jan 2020 10:02:03 -0800 Message-Id: <1580234527-29280-1-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 X-ClientProxiedBy: CO1PR15CA0102.namprd15.prod.outlook.com (2603:10b6:101:21::22) To DM6PR13MB2442.namprd13.prod.outlook.com (2603:10b6:5:cb::25) MIME-Version: 1.0 Received: from gamma07.internal.sifive.com (64.62.193.194) by CO1PR15CA0102.namprd15.prod.outlook.com (2603:10b6:101:21::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2665.22 via Frontend Transport; Tue, 28 Jan 2020 18:02:20 +0000 X-Mailer: git-send-email 2.7.4 X-Originating-IP: [64.62.193.194] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6b193f08-2b86-468e-c777-08d7a41c3873 X-MS-TrafficTypeDiagnostic: DM6PR13MB3803: X-LD-Processed: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1,ExtAddr X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:211; 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Also there are few patches about to go in mainline (Thanks to Jagan Tekki and Bin Meng). This series addresses few issues discussed there: Patch 1:Add num-cs to device tree which is used by spi-uclass to detect valid chip select numbers Patch 2:Handles valid chip selects only. Flash device is now detected only on chip select 0. Patch 3:Over-ride spi tx/rx width specified in hifive-unleshed-a00.dts file from 4 to 1 in corresponding -u-boot.dtsi This series is based on mainline commit c05b38df477a ("common: fix regression on block cache init") and two below mentioned patches from [1] [U-Boot,v2,4/5] riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi [U-Boot,v2,5/5] sifive: fu540: Enable spi-nor flash support [1] https://patchwork.ozlabs.org/patch/1177979/ The above series is available for testing here[2] [2] https://github.com/sagsifive/u-boot/tree/dev/sagark/test_spi-nor_v2 Change History: V1-V2: 1. Dropped 6th and 7th patch sent in V1 from this series so as to separate out spi-nor related changes in different series and avoid adding TODO fixes to spi-nor-core framework. 2. Removed patch to include -uboot.dts, as it gets automatically included. 3. Over-ride tx/rx width from hifive-unleashed-a00.dts using hifive -unleashed-a00-u-boot.dtsi 4. Print fdt base address in board info for debugging. V1: First version of series ================Log for reference===================== Flash detection only at valid Chip select => sf probe 0:0 SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB => sf probe 0:1 Invalid cs number = 1 Failed to initialize SPI flash at 0:1 (error -22) => sf probe 0:2 Invalid cs number = 2 Failed to initialize SPI flash at 0:2 (error -22) => sf probe 0:0 SF: Detected is25wp256 with page size 256 Bytes, erase size 4 KiB, total 32 MiB =>---------------------------------------------------------------- Full flash memory erase/write/read/validate => mw 0x80600000 0x12348765 0x800000 => sf erase 0x0 0x2000000 SF: 33554432 bytes @ 0x0 Erased: OK => sf write 0x80600000 0x0 0x2000000 device 0 whole chip SF: 33554432 bytes @ 0x0 Written: OK => sf read 0x82600000 0x0 0x2000000 device 0 whole chip SF: 33554432 bytes @ 0x0 Read: OK => cmp.b 0x80600000 0x82600000 0x2000000 Total of 33554432 byte(s) were the same =>---------------------------------------------------------------- Sagar Shrikant Kadam (4): fu540: dtsi: spi: add num-cs info to device tree spi: fu540: add claim and release method to spi-sifive.c dts: u-boot.dtsi: override flash tx-rx width bdinfo: fu540: print fdt base address for debugging arch/riscv/dts/fu540-c000.dtsi | 3 +++ arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 8 ++++++ cmd/bdinfo.c | 1 + drivers/spi/spi-sifive.c | 36 +++++++++++++++++++++++++ 4 files changed, 48 insertions(+)