From patchwork Wed Apr 22 19:40:42 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vince Weaver X-Patchwork-Id: 26331 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@bilbo.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from ozlabs.org (ozlabs.org [203.10.76.45]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "mx.ozlabs.org", Issuer "CA Cert Signing Authority" (verified OK)) by bilbo.ozlabs.org (Postfix) with ESMTPS id 69CD5B7043 for ; Thu, 23 Apr 2009 06:09:07 +1000 (EST) Received: by ozlabs.org (Postfix) id 5B9B0DE10E; Thu, 23 Apr 2009 06:09:07 +1000 (EST) Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by ozlabs.org (Postfix) with ESMTP id 02CE7DDEEB for ; Thu, 23 Apr 2009 06:09:07 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752553AbZDVUJE (ORCPT ); Wed, 22 Apr 2009 16:09:04 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752805AbZDVUJE (ORCPT ); Wed, 22 Apr 2009 16:09:04 -0400 Received: from fbr02.csee.onr.siteprotect.com ([64.26.60.146]:60355 "EHLO fbr02.csee.onr.siteprotect.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752553AbZDVUJD (ORCPT ); Wed, 22 Apr 2009 16:09:03 -0400 X-Greylist: delayed 1898 seconds by postgrey-1.27 at vger.kernel.org; Wed, 22 Apr 2009 16:09:03 EDT Received: from smtpauth01.csee.onr.siteprotect.com (smtpauth01.csee.onr.siteprotect.com [64.26.60.145]) by fbr02.csee.onr.siteprotect.com (Postfix) with ESMTP id 7CC2C3D000B for ; Wed, 22 Apr 2009 14:37:59 -0500 (CDT) Received: from pianoman.cluster.toy (unknown [72.81.230.17]) (Authenticated sender: vince@deater.net) by smtpauth01.csee.onr.siteprotect.com (Postfix) with ESMTP id ADC141C8089 for ; Wed, 22 Apr 2009 14:37:23 -0500 (CDT) Date: Wed, 22 Apr 2009 15:40:42 -0400 (EDT) From: Vince Weaver X-X-Sender: vince@pianoman.cluster.toy To: sparclinux@vger.kernel.org Subject: [patch] Niagara1 Perfcounter Accesses Message-ID: MIME-Version: 1.0 Sender: sparclinux-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: sparclinux@vger.kernel.org Add proper Niagara1 perfcounter accesses. When trying to track down the hang-on-boot NMI problem on my T1 system, I noticed that Niagara2 performance counter accesses were being done, even though I only have a Niagara1 system. This means "undefined" bits were being written to in the performance counter register. This patch does not fix the hang, but it's possibly the right thing to do anyway. Signed-off-by: Vince Weaver --- To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/sparc/kernel/pcr.c b/arch/sparc/kernel/pcr.c index 1ae8cdd..bc6c67c 100644 --- a/arch/sparc/kernel/pcr.c +++ b/arch/sparc/kernel/pcr.c @@ -72,11 +72,25 @@ static void n2_pcr_write(u64 val) write_pcr(val); } +static void n1_pcr_write(u64 val) +{ + unsigned long ret; + + ret = sun4v_niagara_setperf(HV_N2_PERF_SPARC_CTL, val); + if (val != HV_EOK) + write_pcr(val); +} + static const struct pcr_ops n2_pcr_ops = { .read = direct_pcr_read, .write = n2_pcr_write, }; +static const struct pcr_ops n1_pcr_ops = { + .read = direct_pcr_read, + .write = n1_pcr_write, +}; + static unsigned long perf_hsvc_group; static unsigned long perf_hsvc_major; static unsigned long perf_hsvc_minor; @@ -126,11 +140,20 @@ int __init pcr_arch_init(void) switch (tlb_type) { case hypervisor: + switch (sun4v_chip_type) { + case SUN4V_CHIP_NIAGARA1: + pcr_ops = &n1_pcr_ops; + pcr_enable = PCR_SUN4U_ENABLE; + break; + + case SUN4V_CHIP_NIAGARA2: pcr_ops = &n2_pcr_ops; pcr_enable = PCR_N2_ENABLE; picl_shift = 2; break; - + } + break; + case cheetah: case cheetah_plus: pcr_ops = &direct_pcr_ops;