From patchwork Wed Feb 1 12:38:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bob Picco X-Patchwork-Id: 722493 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vD2lh1nDVz9ryZ for ; Wed, 1 Feb 2017 23:40:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752136AbdBAMkP (ORCPT ); Wed, 1 Feb 2017 07:40:15 -0500 Received: from userp1040.oracle.com ([156.151.31.81]:50780 "EHLO userp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751927AbdBAMkP (ORCPT ); Wed, 1 Feb 2017 07:40:15 -0500 Received: from userv0022.oracle.com (userv0022.oracle.com [156.151.31.74]) by userp1040.oracle.com (Sentrion-MTA-4.3.2/Sentrion-MTA-4.3.2) with ESMTP id v11Ce6D8003554 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 1 Feb 2017 12:40:07 GMT Received: from userv0121.oracle.com (userv0121.oracle.com [156.151.31.72]) by userv0022.oracle.com (8.14.4/8.14.4) with ESMTP id v11Ce677030172 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 1 Feb 2017 12:40:06 GMT Received: from abhmp0009.oracle.com (abhmp0009.oracle.com [141.146.116.15]) by userv0121.oracle.com (8.14.4/8.13.8) with ESMTP id v11Ce6td007413; Wed, 1 Feb 2017 12:40:06 GMT Received: from oracle.com (/73.38.148.67) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Wed, 01 Feb 2017 04:40:05 -0800 From: Bob Picco To: sparclinux@vger.kernel.org Cc: David Miller , bob picco Subject: [PATCH 1/3] sparc64: make tsb pointer computation symbolic Date: Wed, 1 Feb 2017 07:38:21 -0500 Message-Id: <20170201123823.6273-2-bob.picco@oracle.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170201123823.6273-1-bob.picco@oracle.com> References: <20170201123823.6273-1-bob.picco@oracle.com> X-Source-IP: userv0022.oracle.com [156.151.31.74] Sender: sparclinux-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: sparclinux@vger.kernel.org From: bob picco Define some symbolic names for tsb/tlb miss trap tsb pointer computation. Signed-off-by: Bob Picco --- arch/sparc/include/asm/spitfire.h | 5 +++++ arch/sparc/kernel/sun4v_tlb_miss.S | 24 ++++++++++++------------ 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/arch/sparc/include/asm/spitfire.h b/arch/sparc/include/asm/spitfire.h index 1d8321c827a8..1852a8618001 100644 --- a/arch/sparc/include/asm/spitfire.h +++ b/arch/sparc/include/asm/spitfire.h @@ -37,6 +37,11 @@ #define SPITFIRE_HIGHEST_LOCKED_TLBENT (64 - 1) #define CHEETAH_HIGHEST_LOCKED_TLBENT (16 - 1) +#define HV_TSB_SIZE_BASE 0x200 /* 512 TTE-s minimum. */ +#define HV_TSB_SIZE_BASE_SHIFT 0x09 /* Shift of minimum tsb size. */ +#define HV_TSB_SIZE_MASK 0x07 /* Size encoding of tsb. */ +#define HV_TSB_TTE_SIZE_SHIFT 0x04 /* Sixteen byte tte size. */ + #define L1DCACHE_SIZE 0x4000 #define SUN4V_CHIP_INVALID 0x00 diff --git a/arch/sparc/kernel/sun4v_tlb_miss.S b/arch/sparc/kernel/sun4v_tlb_miss.S index 6179e19bc9b9..8206f5853866 100644 --- a/arch/sparc/kernel/sun4v_tlb_miss.S +++ b/arch/sparc/kernel/sun4v_tlb_miss.S @@ -27,20 +27,20 @@ /* Create TSB pointer. This is something like: * - * index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL; - * tsb_base = tsb_reg & ~0x7UL; + * tsb_mask = (HV_TSB_SIZE_BASE << (tsb_reg & HV_TSB_SIZE_MASK)) - 1UL; + * tsb_base = tsb_reg & ~HV_TSB_SIZE_MASK; * tsb_index = ((vaddr >> HASH_SHIFT) & tsb_mask); - * tsb_ptr = tsb_base + (tsb_index * 16); + * tsb_ptr = tsb_base + (tsb_index * (1UL << HV_TSB_TTE_SIZE_SHIFT)); */ -#define COMPUTE_TSB_PTR(TSB_PTR, VADDR, HASH_SHIFT, TMP1, TMP2) \ - and TSB_PTR, 0x7, TMP1; \ - mov 512, TMP2; \ - andn TSB_PTR, 0x7, TSB_PTR; \ - sllx TMP2, TMP1, TMP2; \ - srlx VADDR, HASH_SHIFT, TMP1; \ - sub TMP2, 1, TMP2; \ - and TMP1, TMP2, TMP1; \ - sllx TMP1, 4, TMP1; \ +#define COMPUTE_TSB_PTR(TSB_PTR, VADDR, HASH_SHIFT, TMP1, TMP2) \ + and TSB_PTR, HV_TSB_SIZE_MASK, TMP1; \ + mov HV_TSB_SIZE_BASE, TMP2; \ + andn TSB_PTR, HV_TSB_SIZE_MASK, TSB_PTR; \ + sllx TMP2, TMP1, TMP2; \ + srlx VADDR, HASH_SHIFT, TMP1; \ + sub TMP2, 1, TMP2; \ + and TMP1, TMP2, TMP1; \ + sllx TMP1, HV_TSB_TTE_SIZE_SHIFT, TMP1; \ add TSB_PTR, TMP1, TSB_PTR; sun4v_itlb_miss: