@@ -36,6 +36,16 @@ static inline notrace void arch_local_irq_restore(unsigned long flags)
);
}
+static inline notrace void arch_local_nmi_disable(void)
+{
+ __asm__ __volatile__(
+ "wrpr %0, %%pil"
+ : /* no outputs */
+ : "i" (PIL_NMI)
+ : "memory"
+ );
+}
+
static inline notrace void arch_local_irq_disable(void)
{
__asm__ __volatile__(
@@ -112,6 +112,7 @@ static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, str
* cpu0 to update it's TSB because at that point the cpu_vm_mask
* only had cpu1 set in it.
*/
+ arch_local_nmi_disable();
load_secondary_context(mm);
tsb_context_switch(mm);
@@ -35,6 +35,7 @@ void restore_processor_state(void)
{
struct mm_struct *mm = current->active_mm;
+ arch_local_nmi_disable();
load_secondary_context(mm);
tsb_context_switch(mm);
}