From patchwork Wed Dec 12 06:58:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Donnellan X-Patchwork-Id: 1011596 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43F748399zz9s47 for ; Wed, 12 Dec 2018 18:00:24 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=au1.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43F7481HR5zDqvN for ; Wed, 12 Dec 2018 18:00:24 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=au1.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=au1.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=andrew.donnellan@au1.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=au1.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43F73B4WmnzDqgl for ; Wed, 12 Dec 2018 17:59:34 +1100 (AEDT) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id wBC6xKFb041124 for ; Wed, 12 Dec 2018 01:59:32 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2pau8nmyt7-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 12 Dec 2018 01:59:32 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 12 Dec 2018 06:59:27 -0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id wBC6xQYg8192484 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 12 Dec 2018 06:59:26 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A203B4204B; Wed, 12 Dec 2018 06:59:26 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0898542042; Wed, 12 Dec 2018 06:59:26 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 12 Dec 2018 06:59:25 +0000 (GMT) Received: from intelligence.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id A1281A030E; Wed, 12 Dec 2018 17:59:24 +1100 (AEDT) From: Andrew Donnellan To: skiboot@lists.ozlabs.org Date: Wed, 12 Dec 2018 17:58:47 +1100 X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-TM-AS-GCONF: 00 x-cbid: 18121206-0016-0000-0000-000002354A7F X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18121206-0017-0000-0000-0000328D7BCB Message-Id: <8e7850ca3aa8928a3e93164ed5a3147cbd79afe5.1544597914.git-series.andrew.donnellan@au1.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-12-12_01:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1812120061 Subject: [Skiboot] [PATCH 04/13] hw/npu2: Simplify npu2_write_bar() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au, arbab@linux.ibm.com, fbarrat@linux.vnet.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Now that we've moved most of the BAR assignment code into common code and we have an existing struct npu2 everywhere we need it, we don't need the gcid and scom parameters to npu2_write_bar() any more. Signed-off-by: Andrew Donnellan Reviewed-by: Frederic Barrat --- hw/npu2-common.c | 14 +++++--------- hw/npu2-opencapi.c | 4 ++-- hw/npu2.c | 6 +++--- include/npu2.h | 3 +-- 4 files changed, 11 insertions(+), 16 deletions(-) diff --git a/hw/npu2-common.c b/hw/npu2-common.c index b140e9ffd064..6cbae9bffaf9 100644 --- a/hw/npu2-common.c +++ b/hw/npu2-common.c @@ -141,8 +141,7 @@ void npu2_read_bar(struct npu2 *p, struct npu2_bar *bar) } } -void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar, uint32_t gcid, - uint32_t scom) +void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar) { uint64_t reg, val; int block; @@ -168,10 +167,7 @@ void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar, uint32_t gcid, for (block = NPU2_BLOCK_SM_0; block <= NPU2_BLOCK_SM_3; block++) { reg = NPU2_REG_OFFSET(0, block, bar->reg); - if (p) - npu2_write(p, reg, val); - else - npu2_scom_write(gcid, scom, reg, NPU2_MISC_DA_LEN_8B, val); + npu2_write(p, reg, val); } } @@ -200,7 +196,7 @@ static void assign_bars(struct npu2 *npu) for (i = 0; i < ARRAY_SIZE(phy_bars); i++) { bar = &phy_bars[i]; npu2_get_bar(npu->chip_id, bar); - npu2_write_bar(npu, bar, npu->chip_id, npu->xscom_base); + npu2_write_bar(npu, bar); } /* Device BARs */ @@ -221,7 +217,7 @@ static void assign_bars(struct npu2 *npu) NPU2_NTL0_BAR : NPU2_NTL1_BAR); bar->flags = PCI_CFG_BAR_TYPE_MEM | PCI_CFG_BAR_MEM64; npu2_get_bar(npu->chip_id, bar); - npu2_write_bar(npu, bar, npu->chip_id, npu->xscom_base); + npu2_write_bar(npu, bar); /* GENID BAR */ bar = &dev->genid_bar; @@ -234,7 +230,7 @@ static void assign_bars(struct npu2 *npu) bar->size = 0x10000; if (NPU2DEV_BRICK(dev)) bar->base += 0x10000; - npu2_write_bar(npu, bar, npu->chip_id, npu->xscom_base); + npu2_write_bar(npu, bar); }; /* Global MMIO BAR */ diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index b374a1035ac9..cc7c403351ce 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -742,7 +742,7 @@ static void setup_afu_mmio_bars(uint32_t gcid, uint32_t scom_base, prlog(PR_DEBUG, "OCAPI: %s: Setup AFU MMIO BARs\n", __func__); dev->ntl_bar.enabled = true; - npu2_write_bar(dev->npu, &dev->ntl_bar, gcid, scom_base); + npu2_write_bar(dev->npu, &dev->ntl_bar); reg = SETFIELD(NPU2_CQ_CTL_MISC_MMIOPA_ADDR, 0ull, dev->ntl_bar.base >> 16); reg = SETFIELD(NPU2_CQ_CTL_MISC_MMIOPA_SIZE, reg, ilog2(dev->ntl_bar.size >> 16)); @@ -1578,7 +1578,7 @@ static void setup_device(struct npu2_dev *dev) setup_afu_mmio_bars(dev->npu->chip_id, dev->npu->xscom_base, dev); /* Procedure 13.1.3.9 - AFU Config BARs */ dev->genid_bar.enabled = true; - npu2_write_bar(dev->npu, &dev->genid_bar, dev->npu->chip_id, dev->npu->xscom_base); + npu2_write_bar(dev->npu, &dev->genid_bar); set_fence_control(dev->npu->chip_id, dev->npu->xscom_base, dev->brick_index, 0b00); diff --git a/hw/npu2.c b/hw/npu2.c index 6aa16a43f803..1e9fb581688f 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -131,7 +131,7 @@ static int64_t npu2_cfg_write_cmd(void *dev, enabled = !!(*data & PCI_CFG_CMD_MEM_EN); ndev->ntl_bar.enabled = enabled; - npu2_write_bar(ndev->npu, &ndev->ntl_bar, 0, 0); + npu2_write_bar(ndev->npu, &ndev->ntl_bar); /* * Enable/disable the GENID BAR. Two bricks share one GENID @@ -146,7 +146,7 @@ static int64_t npu2_cfg_write_cmd(void *dev, /* Enable the BAR if either device requests it enabled, otherwise disable it */ ndev->genid_bar.enabled = ndev->genid_bar.enabled0 || ndev->genid_bar.enabled1; - npu2_write_bar(ndev->npu, &ndev->genid_bar, 0, 0); + npu2_write_bar(ndev->npu, &ndev->genid_bar); return OPAL_PARTIAL; } @@ -220,7 +220,7 @@ static int64_t npu2_cfg_write_bar(struct npu2_dev *dev, return OPAL_HARDWARE; } - npu2_write_bar(dev->npu, bar, 0, 0); + npu2_write_bar(dev->npu, bar); } /* To update the config cache */ diff --git a/include/npu2.h b/include/npu2.h index bf7fb6927dd4..64be9f4eb9dd 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -214,8 +214,7 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); void npu2_write_mask_4b(struct npu2 *p, uint64_t reg, uint32_t val, uint32_t mask); void npu2_get_bar(uint32_t gcid, struct npu2_bar *bar); void npu2_read_bar(struct npu2 *p, struct npu2_bar *bar); -void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar, uint32_t gcid, - uint32_t scom); +void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar); int64_t npu2_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf, uint32_t offset, uint32_t len, uint32_t *data, bool write);