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[121.44.67.22]) by smtp.gmail.com with ESMTPSA id p17sm20661731pfh.86.2021.12.20.04.23.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Dec 2021 04:23:14 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Mon, 20 Dec 2021 22:22:48 +1000 Message-Id: <20211220122252.986542-6-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211220122252.986542-1-npiggin@gmail.com> References: <20211220122252.986542-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v5 5/9] hw/slw: Move P8 bits behind CONFIG_P8 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This saves about 10kB from skiboot.lid.xz Reviewed-by: Dan Horák Signed-off-by: Nicholas Piggin --- core/fast-reboot.c | 2 + hw/Makefile.inc | 4 +- hw/sbe.c | 2 + hw/slw.c | 176 ++++++++++++++++++++++--------------------- libpore/Makefile.inc | 8 +- 5 files changed, 104 insertions(+), 88 deletions(-) diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 9f92525a9..2696348af 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -272,6 +272,7 @@ static void cleanup_cpu_state(void) /* XXX Update the SLW copies ! Also dbl check HIDs etc... */ init_shared_sprs(); +#ifdef CONFIG_P8 if (proc_gen == proc_gen_p8) { /* If somebody was in fast_sleep, we may have a * workaround to undo @@ -287,6 +288,7 @@ static void cleanup_cpu_state(void) */ cleanup_local_tlb(); } +#endif /* And we might have lost TB sync */ chiptod_wakeup_resync(); diff --git a/hw/Makefile.inc b/hw/Makefile.inc index a6732b7bc..8f509739d 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -7,10 +7,10 @@ HW_OBJS += sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o -HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o +HW_OBJS += occ-sensor.o vas.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += npu-opal.o ocmb.o xive2.o pau.o pau-hw-procedures.o ifeq ($(CONFIG_P8),1) -HW_OBJS += phb3.o +HW_OBJS += phb3.o sbe-p8.o endif HW=hw/built-in.a diff --git a/hw/sbe.c b/hw/sbe.c index 991485e5b..859581662 100644 --- a/hw/sbe.c +++ b/hw/sbe.c @@ -21,8 +21,10 @@ void sbe_update_timer_expiry(uint64_t target) if (proc_gen == proc_gen_p9 || proc_gen == proc_gen_p10) p9_sbe_update_timer_expiry(target); +#ifdef CONFIG_P8 if (proc_gen == proc_gen_p8) p8_sbe_update_timer_expiry(target); +#endif } bool sbe_timer_ok(void) diff --git a/hw/slw.c b/hw/slw.c index eb67998d1..bc53960b7 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -32,19 +32,20 @@ enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; bool has_deep_states = false; -DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, - OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL, - OPAL_NA); - DEFINE_LOG_ENTRY(OPAL_RC_SLW_SET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); -DEFINE_LOG_ENTRY(OPAL_RC_SLW_GET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, +DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); -DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, +#ifdef CONFIG_P8 +DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, + OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL, + OPAL_NA); + +DEFINE_LOG_ENTRY(OPAL_RC_SLW_GET, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); @@ -98,59 +99,6 @@ static bool slw_set_overrides(struct proc_chip *chip, struct cpu_thread *c) return true; } -static bool slw_set_overrides_p10(struct proc_chip *chip, struct cpu_thread *c) -{ - uint64_t tmp; - int rc; - uint32_t core = pir_to_core_id(c->pir); - - /* Special wakeup bits that could hold power mgt */ - rc = xscom_read(chip->id, - XSCOM_ADDR_P10_QME_CORE(core, P10_QME_SPWU_HYP), - &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_SET), - "SLW: Failed to read P10_QME_SPWU_HYP\n"); - return false; - } - if (tmp & P10_SPWU_REQ) - prlog(PR_WARNING, - "SLW: core %d P10_QME_SPWU_HYP requested 0x%016llx\n", - core, tmp); - - return true; -} - - -static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) -{ - uint64_t tmp; - int rc; - uint32_t core = pir_to_core_id(c->pir); - - /* Special wakeup bits that could hold power mgt */ - rc = xscom_read(chip->id, - XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP), - &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_SET), - "SLW: Failed to read EC_PPM_SPECIAL_WKUP_HYP\n"); - return false; - } - if (tmp) - prlog(PR_WARNING, - "SLW: core %d EC_PPM_SPECIAL_WKUP_HYP read 0x%016llx\n", - core, tmp); - rc = xscom_read(chip->id, - XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_OTR), - &tmp); - if (tmp) - prlog(PR_WARNING, - "SLW: core %d EC_PPM_SPECIAL_WKUP_OTR read 0x%016llx\n", - core, tmp); - return true; -} - static bool slw_set_idle_mode(struct proc_chip *chip, struct cpu_thread *c) { uint32_t core = pir_to_core_id(c->pir); @@ -242,6 +190,60 @@ static bool idle_prepare_core(struct proc_chip *chip, struct cpu_thread *c) return true; } +#endif + +static bool slw_set_overrides_p10(struct proc_chip *chip, struct cpu_thread *c) +{ + uint64_t tmp; + int rc; + uint32_t core = pir_to_core_id(c->pir); + + /* Special wakeup bits that could hold power mgt */ + rc = xscom_read(chip->id, + XSCOM_ADDR_P10_QME_CORE(core, P10_QME_SPWU_HYP), + &tmp); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_SET), + "SLW: Failed to read P10_QME_SPWU_HYP\n"); + return false; + } + if (tmp & P10_SPWU_REQ) + prlog(PR_WARNING, + "SLW: core %d P10_QME_SPWU_HYP requested 0x%016llx\n", + core, tmp); + + return true; +} + + +static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) +{ + uint64_t tmp; + int rc; + uint32_t core = pir_to_core_id(c->pir); + + /* Special wakeup bits that could hold power mgt */ + rc = xscom_read(chip->id, + XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_HYP), + &tmp); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_SET), + "SLW: Failed to read EC_PPM_SPECIAL_WKUP_HYP\n"); + return false; + } + if (tmp) + prlog(PR_WARNING, + "SLW: core %d EC_PPM_SPECIAL_WKUP_HYP read 0x%016llx\n", + core, tmp); + rc = xscom_read(chip->id, + XSCOM_ADDR_P9_EC_SLAVE(core, EC_PPM_SPECIAL_WKUP_OTR), + &tmp); + if (tmp) + prlog(PR_WARNING, + "SLW: core %d EC_PPM_SPECIAL_WKUP_OTR read 0x%016llx\n", + core, tmp); + return true; +} /* Define device-tree fields */ #define MAX_NAME_LEN 16 @@ -1069,31 +1071,6 @@ void add_cpu_idle_state_properties(void) free(pm_ctrl_reg_mask_buf); } -static void slw_patch_regs(struct proc_chip *chip) -{ - struct cpu_thread *c; - void *image = (void *)chip->slw_base; - int rc; - - for_each_available_cpu(c) { - if (c->chip_id != chip->id) - continue; - - /* Clear HRMOR */ - rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, - P8_SPR_HRMOR, 0, - cpu_get_core_index(c), - cpu_get_thread_index(c)); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to set HRMOR for CPU %x\n", - c->pir); - } - - /* XXX Add HIDs etc... */ - } -} - static void slw_init_chip_p9(struct proc_chip *chip) { struct cpu_thread *c; @@ -1135,6 +1112,32 @@ static bool slw_image_check_p9(struct proc_chip *chip) } +#ifdef CONFIG_P8 +static void slw_patch_regs(struct proc_chip *chip) +{ + struct cpu_thread *c; + void *image = (void *)chip->slw_base; + int rc; + + for_each_available_cpu(c) { + if (c->chip_id != chip->id) + continue; + + /* Clear HRMOR */ + rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, + P8_SPR_HRMOR, 0, + cpu_get_core_index(c), + cpu_get_thread_index(c)); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: Failed to set HRMOR for CPU %x\n", + c->pir); + } + + /* XXX Add HIDs etc... */ + } +} + static bool slw_image_check_p8(struct proc_chip *chip) { int64_t rc; @@ -1284,6 +1287,7 @@ static int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t enter) } opal_call(OPAL_CONFIG_CPU_IDLE_STATE, opal_config_cpu_idle_state, 2); +#endif int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) { @@ -1324,6 +1328,7 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) sprn, val, cpu_pir); } +#ifdef CONFIG_P8 } else if (proc_gen == proc_gen_p8) { int spr_is_supported = 0; void *image; @@ -1347,6 +1352,7 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) sprn, val, cpu_get_core_index(c), cpu_get_thread_index(c)); +#endif } else { log_simple_error(&e_info(OPAL_RC_SLW_REG), "SLW: proc_gen not supported\n"); @@ -1381,6 +1387,7 @@ void slw_init(void) } if (proc_gen == proc_gen_p8) { +#ifdef CONFIG_P8 for_each_chip(chip) { slw_init_chip_p8(chip); if(slw_image_check_p8(chip)) @@ -1389,6 +1396,7 @@ void slw_init(void) slw_late_init_p8(chip); } p8_sbe_init_timer(); +#endif } else if (proc_gen == proc_gen_p9) { for_each_chip(chip) { slw_init_chip_p9(chip); diff --git a/libpore/Makefile.inc b/libpore/Makefile.inc index 06d9c8902..76c30d426 100644 --- a/libpore/Makefile.inc +++ b/libpore/Makefile.inc @@ -1,5 +1,9 @@ -LIBPORE_SRCS = p8_pore_table_gen_api_fixed.C p9_stop_api.C p9_stop_util.C p10_stop_api.C p10_stop_util.C -LIBPORE_SRCS += p8_pore_table_static_data.c sbe_xip_image.c pore_inline_assembler.c +LIBPORE_SRCS = p9_stop_api.C p9_stop_util.C p10_stop_api.C p10_stop_util.C +ifeq ($(CONFIG_P8),1) +LIBPORE_SRCS += sbe_xip_image.c pore_inline_assembler.c +LIBPORE_SRCS += p8_pore_table_gen_api_fixed.C p8_pore_table_static_data.c +endif + LIBPORE_OBJS_1 = $(LIBPORE_SRCS:%.c=%.o) LIBPORE_OBJS = $(LIBPORE_OBJS_1:%.C=%.o) SUBDIRS += libpore