diff mbox series

[v5,3/9] Add CONFIG_P8 with PHB3 behind it

Message ID 20211220122252.986542-4-npiggin@gmail.com
State Accepted
Headers show
Series hwprobe patches | expand

Commit Message

Nicholas Piggin Dec. 20, 2021, 12:22 p.m. UTC 
From: Stewart Smith <stewart@flamingspork.com>

We can use a base CPU of POWER9 if we don't have P8.
We can also hide PHB3 code behind this,
and shave 12kb off skiboot.lid.xz

Reviewed-by: Dan Horák <dan@danny.cz>
[npiggin: add cpp define, fail gracefully on P8]
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
---
 Makefile        |  2 ++
 Makefile.main   | 15 ++++++++++++++-
 core/cpu.c      | 11 +++++++++--
 hw/Makefile.inc |  5 ++++-
 4 files changed, 29 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/Makefile b/Makefile
index d236df9ec..625f212ea 100644
--- a/Makefile
+++ b/Makefile
@@ -59,6 +59,8 @@  ELF_ABI_v2 ?= $(LITTLE_ENDIAN)
 DEAD_CODE_ELIMINATION ?= 0
 # Try to build without FSP code
 CONFIG_FSP?=1
+# Try to build without POWER8 support
+CONFIG_P8?=1
 
 #
 # Where is the source directory, must be a full path (no ~)
diff --git a/Makefile.main b/Makefile.main
index c8a63e8b1..2a346a6c9 100644
--- a/Makefile.main
+++ b/Makefile.main
@@ -96,7 +96,11 @@  CPPFLAGS += -DDEBUG -DCCAN_LIST_DEBUG
 endif
 
 CFLAGS := -fno-strict-aliasing -pie -fpie -fno-pic -m64 -fno-asynchronous-unwind-tables
+ifeq ($(CONFIG_P8),1)
 CFLAGS += -mcpu=power8
+else
+CFLAGS += -mcpu=power9
+endif
 CFLAGS += -Wl,--oformat,elf64-powerpc -ggdb
 # r13,r14,r15 are preserved for OS to use as fixed registers.
 # These could be saved and restored in and out of skiboot, but it's more
@@ -156,6 +160,10 @@  else
 CFLAGS += -fno-stack-protector
 endif
 
+# Add preprocessor defines for CONFIG_ options here
+ifeq ($(CONFIG_P8),1)
+CFLAGS += -DCONFIG_P8=1
+endif
 
 CFLAGS += $(call try-cflag,$(CC),-Wjump-misses-init) \
 	  $(call try-cflag,$(CC),-Wsuggest-attribute=const) \
@@ -173,7 +181,12 @@  LDFLAGS := -m64 -static -nostdlib -pie
 LDFLAGS += -Wl,-pie
 LDFLAGS += -Wl,-Ttext-segment,$(LD_TEXT) -Wl,-N -Wl,--build-id=none
 LDFLAGS += -Wl,--no-multi-toc
-LDFLAGS += -mcpu=power8 -Wl,--oformat,elf64-powerpc
+ifeq ($(CONFIG_P8),1)
+LDFLAGS += -mcpu=power8
+else
+LDFLAGS += -mcpu=power9
+endif
+LDFLAGS += -Wl,--oformat,elf64-powerpc
 LDFLAGS_FINAL = -m elf64lppc --no-multi-toc -N --build-id=none --whole-archive
 LDFLAGS_FINAL += -static -nostdlib -pie -Ttext-segment=$(LD_TEXT) --oformat=elf64-powerpc
 LDFLAGS_FINAL += --orphan-handling=warn
diff --git a/core/cpu.c b/core/cpu.c
index 6756ab164..f0be58059 100644
--- a/core/cpu.c
+++ b/core/cpu.c
@@ -1066,9 +1066,16 @@  void init_boot_cpu(void)
 		cpu_thread_count = 1;
 	}
 
-	if (proc_gen == proc_gen_p8 && (PVR_VERS_MAJ(mfspr(SPR_PVR)) == 1)) {
-		prerror("CPU: POWER8 DD1 is not supported\n");
+	if (proc_gen == proc_gen_p8) {
+#ifdef CONFIG_P8
+		if (PVR_VERS_MAJ(mfspr(SPR_PVR)) == 1) {
+			prerror("CPU: POWER8 DD1 is not supported\n");
+			abort();
+		}
+#else
+		prerror("CPU: POWER8 detected but CONFIG_P8 not set\n");
 		abort();
+#endif
 	}
 
 	if (is_power9n(pvr) && (PVR_VERS_MAJ(pvr) == 1)) {
diff --git a/hw/Makefile.inc b/hw/Makefile.inc
index 9fcbb63be..e273e898c 100644
--- a/hw/Makefile.inc
+++ b/hw/Makefile.inc
@@ -3,12 +3,15 @@  SUBDIRS += hw
 HW_OBJS  = xscom.o chiptod.o lpc.o lpc-uart.o psi.o
 HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o imc.o
 HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o nx-gzip.o
-HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o
+HW_OBJS += sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o
 HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o
 HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o
 HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o
 HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o
 HW_OBJS += npu-opal.o ocmb.o xive2.o pau.o pau-hw-procedures.o
+ifeq ($(CONFIG_P8),1)
+HW_OBJS += phb3.o
+endif
 HW=hw/built-in.a
 
 include $(SRC)/hw/fsp/Makefile.inc