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[203.219.139.206]) by smtp.gmail.com with ESMTPSA id k22sm7638186pfu.72.2021.12.16.18.24.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Dec 2021 18:24:44 -0800 (PST) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Fri, 17 Dec 2021 12:24:39 +1000 Message-Id: <20211217022439.709659-1-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Subject: [Skiboot] [RFC PATCH] chiptod: properly zero TB SPR when cleaning up for invalid TB X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The existing sequence writes TBU twice and leaves TBL unchanged. This may not really matter if it's being resynced from the chiptod soon, but it's possible it could clear a parity error. Signed-off-by: Nicholas Piggin Reviewed-by: Cédric Le Goater --- I did not find the recovery recipe or reason to clear TBU twice in the workbook. So it looks odd and the new sequence follows the ISA requirement to zero the TB register, but maybe I overlook something. If 2x mfTBU is required then it should have a comment IMO. hw/chiptod.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/chiptod.c b/hw/chiptod.c index 7c0a1ffc7..736bd03fa 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -1556,8 +1556,9 @@ void tfmr_cleanup_core_errors(uint64_t tfmr) * restored after the next rendez-vous */ if (!(tfmr & SPR_TFMR_TB_VALID)) { + mtspr(SPR_TBWL, 0); mtspr(SPR_TBWU, 0); - mtspr(SPR_TBWU, 0); + mtspr(SPR_TBWL, 0); } }