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[115.64.153.41]) by smtp.gmail.com with ESMTPSA id z3sm11158058pfe.78.2021.10.02.18.22.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Oct 2021 18:22:23 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Sun, 3 Oct 2021 11:22:06 +1000 Message-Id: <20211003012210.1165606-5-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20211003012210.1165606-1-npiggin@gmail.com> References: <20211003012210.1165606-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 4/8] asm/head: Fix P10 HILE for little endian build X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Fixes: 891ed8df67 ("Initial POWER10 enablement") Signed-off-by: Nicholas Piggin --- asm/head.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/asm/head.S b/asm/head.S index fa8933b14..b2755344d 100644 --- a/asm/head.S +++ b/asm/head.S @@ -829,8 +829,13 @@ init_shared_sprs: /* HID0: * Boot with PPC_BIT(5) set (dis_recovery). * Leave bit 5 set to disable recovery (due to HW570622) + * Set/clear bit 4 (HILE) depending on skiboot endian */ +#if HAVE_BIG_ENDIAN LOAD_IMM64(%r3, PPC_BIT(5)) +#else + LOAD_IMM64(%r3, PPC_BIT(5) | PPC_BIT(4)) +#endif sync mtspr SPR_HID0,%r3 isync