From patchwork Wed Aug 11 05:46:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1515576 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ALBUH//F; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GkzNt2yWrz9sWS for ; Wed, 11 Aug 2021 15:47:26 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4GkzNt1QHDz30JK for ; Wed, 11 Aug 2021 15:47:26 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ALBUH//F; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::629; helo=mail-pl1-x629.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=ALBUH//F; dkim-atps=neutral Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4GkzNg09hJz309L for ; Wed, 11 Aug 2021 15:47:14 +1000 (AEST) Received: by mail-pl1-x629.google.com with SMTP id d17so1206929plr.12 for ; Tue, 10 Aug 2021 22:47:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LYCp6Euu7h93v8gSEOwy8OByKSI5Lycz3xb3efU2nTY=; b=ALBUH//FxuZ+QyCe6r3BTGtunnvukpVFR+7NQDwqXHZca1C+iEmahl4QNyfOAUfNDB rrsBV+GP1u+tttU/jmSSukBHVTQe+uQ/+gAdyn97A6KlYWdtvdROtH65E3fkH4uA18WD HK9udr8OmOzNjwjjP0Orjnq9USMLrXQH+T69+JGkJDt+YMvXfdNtrGPkRSmF6reg5cKS WjWzPQbHD45HxodlMXw589Siaxf6kKqjwXyDj1QS/MqaVmYubLBbtJuvQ5d9zPxIJ5Nu 6em2lbgCcHzpNRNaqhPJO4+T1/K5ngsYV/NNDAJreUAZwGfTHkY3c4MsOW9Id2b0ZhBj zosw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LYCp6Euu7h93v8gSEOwy8OByKSI5Lycz3xb3efU2nTY=; b=Ds65C1GbK0FQyiaxBwmppKAuaoby/LLGjwiVzdqfm+XI+GKWCN0LK1YwovcXyNY2Dn KBAj3B9z4pWow+jyqZd8J+yDcLYCQycyEhS9wTfA9LG2tQWoNVspICyNra6qSJycJcik Vx2wiUhvGBsghHDS4xrGyATHGst4lzZdOe4ETjPYYbMvqMK6Sk1inpl1CfekY++6vznb 2jzwugtRWHr4KOyG+tIhYvlxvHVNAXbw28gwtyGeHlkttYAlK/w0bWMYUp8hPpoHJ9Bs Lhqw+7qyDoMAemXKGdu8XDxlVIuBmgw9rEnRLFlKGh6GPgq0QMdX83ttoYST09XyrthW yUGg== X-Gm-Message-State: AOAM533fj5F9cr+M7TnpsbHSTQNoibkEvL1NRgYRaY77OEhvbcS3Q9/O eCsxE+cilZj/Xsexqw/v979NnX2SphQ= X-Google-Smtp-Source: ABdhPJy2uQvstpoEe/DiEHozDRUM+MTZ2z7fEPx7G5tFOGyY4R0jlLZ7WmxhKsf2mHV06C2I8JdWOw== X-Received: by 2002:a65:6287:: with SMTP id f7mr609374pgv.444.1628660831809; Tue, 10 Aug 2021 22:47:11 -0700 (PDT) Received: from bobo.ibm.com ([118.210.97.79]) by smtp.gmail.com with ESMTPSA id fu10sm14248050pjb.8.2021.08.10.22.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Aug 2021 22:47:11 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Wed, 11 Aug 2021 15:46:52 +1000 Message-Id: <20210811054701.861123-2-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20210811054701.861123-1-npiggin@gmail.com> References: <20210811054701.861123-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH v3 01/10] Remove support for POWER8 DD1 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This significantly simplifies the SLW code. HILE is now always supported. Reviewed-by: Stewart Smith Signed-off-by: Nicholas Piggin --- core/cpu.c | 23 ++-- hw/slw.c | 323 ---------------------------------------------- include/skiboot.h | 5 - 3 files changed, 9 insertions(+), 342 deletions(-) diff --git a/core/cpu.c b/core/cpu.c index f58aeb27a..60a9ea1c3 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -35,7 +35,6 @@ unsigned int cpu_thread_count; unsigned int cpu_max_pir; struct cpu_thread *boot_cpu; static struct lock reinit_lock = LOCK_UNLOCKED; -static bool hile_supported; static bool radix_supported; static unsigned long hid0_hile; static unsigned long hid0_attn; @@ -999,27 +998,23 @@ void init_boot_cpu(void) case PVR_TYPE_P8E: case PVR_TYPE_P8: proc_gen = proc_gen_p8; - hile_supported = PVR_VERS_MAJ(mfspr(SPR_PVR)) >= 2; hid0_hile = SPR_HID0_POWER8_HILE; hid0_attn = SPR_HID0_POWER8_ENABLE_ATTN; break; case PVR_TYPE_P8NVL: proc_gen = proc_gen_p8; - hile_supported = true; hid0_hile = SPR_HID0_POWER8_HILE; hid0_attn = SPR_HID0_POWER8_ENABLE_ATTN; break; case PVR_TYPE_P9: case PVR_TYPE_P9P: proc_gen = proc_gen_p9; - hile_supported = true; radix_supported = true; hid0_hile = SPR_HID0_POWER9_HILE; hid0_attn = SPR_HID0_POWER9_ENABLE_ATTN; break; case PVR_TYPE_P10: proc_gen = proc_gen_p10; - hile_supported = true; radix_supported = true; hid0_hile = SPR_HID0_POWER10_HILE; hid0_attn = SPR_HID0_POWER10_ENABLE_ATTN; @@ -1056,6 +1051,11 @@ void init_boot_cpu(void) cpu_thread_count = 1; } + if (proc_gen == proc_gen_p8 && (PVR_VERS_MAJ(mfspr(SPR_PVR)) == 1)) { + prerror("CPU: POWER8 DD1 is not supported\n"); + abort(); + } + if (is_power9n(pvr) && (PVR_VERS_MAJ(pvr) == 1)) { prerror("CPU: POWER9N DD1 is not supported\n"); abort(); @@ -1597,7 +1597,7 @@ static int64_t opal_reinit_cpus(uint64_t flags) } /* * Now we need to mark ourselves "active" or we'll be skipped - * by the various "for_each_active_..." calls done by slw_reinit() + * by the various "for_each_active_..." */ this_cpu()->state = cpu_state_active; this_cpu()->in_reinit = true; @@ -1611,10 +1611,8 @@ static int64_t opal_reinit_cpus(uint64_t flags) */ cpu_cleanup_all(); - /* If HILE change via HID0 is supported ... */ - if (hile_supported && - (flags & (OPAL_REINIT_CPUS_HILE_BE | - OPAL_REINIT_CPUS_HILE_LE))) { + if (flags & (OPAL_REINIT_CPUS_HILE_BE | + OPAL_REINIT_CPUS_HILE_LE)) { bool hile = !!(flags & OPAL_REINIT_CPUS_HILE_LE); flags &= ~(OPAL_REINIT_CPUS_HILE_BE | OPAL_REINIT_CPUS_HILE_LE); @@ -1669,10 +1667,7 @@ static int64_t opal_reinit_cpus(uint64_t flags) rc = OPAL_SUCCESS; } - /* Handle P8 DD1 SLW reinit */ - if (flags != 0 && proc_gen == proc_gen_p8 && !hile_supported) - rc = slw_reinit(flags); - else if (flags != 0) + if (flags != 0) rc = OPAL_UNSUPPORTED; /* And undo the above */ diff --git a/hw/slw.c b/hw/slw.c index 56ba05b0a..178ee4f85 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -29,10 +29,6 @@ #include #include -static uint32_t slw_saved_reset[0x100]; - -static bool slw_current_le = false; - enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; bool has_deep_states = false; @@ -52,125 +48,6 @@ DEFINE_LOG_ENTRY(OPAL_RC_SLW_REG, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_INFO, OPAL_NA); -static void slw_do_rvwinkle(void *data) -{ - struct cpu_thread *cpu = this_cpu(); - struct cpu_thread *master = data; - uint64_t lpcr = mfspr(SPR_LPCR); - struct proc_chip *chip; - - /* Setup our ICP to receive IPIs */ - icp_prep_for_pm(); - - /* Setup LPCR to wakeup on external interrupts only */ - mtspr(SPR_LPCR, ((lpcr & ~SPR_LPCR_P8_PECE) | SPR_LPCR_P8_PECE2)); - isync(); - - prlog(PR_DEBUG, "SLW: CPU PIR 0x%04x going to rvwinkle...\n", - cpu->pir); - - /* Tell that we got it */ - cpu->state = cpu_state_rvwinkle; - - enter_p8_pm_state(1); - - /* Restore SPRs */ - init_shared_sprs(); - init_replicated_sprs(); - - /* Ok, it's ours again */ - cpu->state = cpu_state_active; - - prlog(PR_DEBUG, "SLW: CPU PIR 0x%04x woken up !\n", cpu->pir); - - /* Cleanup our ICP */ - reset_cpu_icp(); - - /* Resync timebase */ - chiptod_wakeup_resync(); - - /* Restore LPCR */ - mtspr(SPR_LPCR, lpcr); - isync(); - - /* If we are passed a master pointer we are the designated - * waker, let's proceed. If not, return, we are finished. - */ - if (!master) - return; - - prlog(PR_DEBUG, "SLW: CPU PIR 0x%04x waiting for master...\n", - cpu->pir); - - /* Allriiiight... now wait for master to go down */ - while(master->state != cpu_state_rvwinkle) - sync(); - - /* XXX Wait one second ! (should check xscom state ? ) */ - time_wait_ms(1000); - - for_each_chip(chip) { - struct cpu_thread *c; - uint64_t tmp; - for_each_available_core_in_chip(c, chip->id) { - xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir), - EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - prlog(PR_TRACE, "SLW: core %x:%x" - " history: 0x%016llx (mid2)\n", - chip->id, pir_to_core_id(c->pir), - tmp); - } - } - - prlog(PR_DEBUG, "SLW: Waking master (PIR 0x%04x)...\n", master->pir); - - /* Now poke all the secondary threads on the master's core */ - for_each_cpu(cpu) { - if (!cpu_is_sibling(cpu, master) || (cpu == master)) - continue; - icp_kick_cpu(cpu); - - /* Wait for it to claim to be back (XXX ADD TIMEOUT) */ - while(cpu->state != cpu_state_active) - sync(); - } - - /* Now poke the master and be gone */ - icp_kick_cpu(master); -} - -static void slw_patch_reset(void) -{ - uint32_t *src, *dst, *sav; - - src = &reset_patch_start; - dst = (uint32_t *)0x100; - sav = slw_saved_reset; - while(src < &reset_patch_end) { - *(sav++) = *(dst); - *(dst++) = *(src++); - } - sync_icache(); -} - -static void slw_unpatch_reset(void) -{ - extern uint32_t reset_patch_start; - extern uint32_t reset_patch_end; - uint32_t *src, *dst, *sav; - - src = &reset_patch_start; - dst = (uint32_t *)0x100; - sav = slw_saved_reset; - while(src < &reset_patch_end) { - *(dst++) = *(sav++); - src++; - } - sync_icache(); -} - static bool slw_general_init(struct proc_chip *chip, struct cpu_thread *c) { uint32_t core = pir_to_core_id(c->pir); @@ -274,15 +151,6 @@ static bool slw_set_overrides_p9(struct proc_chip *chip, struct cpu_thread *c) return true; } -static bool slw_unset_overrides(struct proc_chip *chip, struct cpu_thread *c) -{ - uint32_t core = pir_to_core_id(c->pir); - - /* XXX FIXME: Save and restore the overrides */ - prlog(PR_DEBUG, "SLW: slw_unset_overrides %x:%x\n", chip->id, core); - return true; -} - static bool slw_set_idle_mode(struct proc_chip *chip, struct cpu_thread *c) { uint32_t core = pir_to_core_id(c->pir); @@ -1201,197 +1069,6 @@ void add_cpu_idle_state_properties(void) free(pm_ctrl_reg_mask_buf); } -static void slw_cleanup_core(struct proc_chip *chip, struct cpu_thread *c) -{ - uint64_t tmp; - int rc; - - /* Display history to check transition */ - rc = xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir), - EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_GET), - "SLW: Failed to read PM_IDLE_STATE_HISTORY\n"); - /* XXX error handling ? return false; */ - } - - prlog(PR_DEBUG, "SLW: core %x:%x history: 0x%016llx (new1)\n", - chip->id, pir_to_core_id(c->pir), tmp); - - rc = xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir), - EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_GET), - "SLW: Failed to read PM_IDLE_STATE_HISTORY\n"); - /* XXX error handling ? return false; */ - } - - prlog(PR_DEBUG, "SLW: core %x:%x history: 0x%016llx (new2)\n", - chip->id, pir_to_core_id(c->pir), tmp); - - /* - * XXX FIXME: Error out if the transition didn't reach rvwinkle ? - */ - - /* - * XXX FIXME: We should restore a bunch of the EX bits we - * overwrite to sane values here - */ - slw_unset_overrides(chip, c); -} - -static void slw_cleanup_chip(struct proc_chip *chip) -{ - struct cpu_thread *c; - - for_each_available_core_in_chip(c, chip->id) - slw_cleanup_core(chip, c); -} - -static void slw_patch_scans(struct proc_chip *chip, bool le_mode) -{ - int64_t rc; - uint64_t old_val, new_val; - - rc = sbe_xip_get_scalar((void *)chip->slw_base, - "skip_ex_override_ring_scans", &old_val); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to read scan override on chip %d\n", - chip->id); - return; - } - - new_val = le_mode ? 0 : 1; - - prlog(PR_TRACE, "SLW: Chip %d, LE value was: %lld, setting to %lld\n", - chip->id, old_val, new_val); - - rc = sbe_xip_set_scalar((void *)chip->slw_base, - "skip_ex_override_ring_scans", new_val); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_REG), - "SLW: Failed to set LE mode on chip %d\n", chip->id); - return; - } -} - -int64_t slw_reinit(uint64_t flags) -{ - struct proc_chip *chip; - struct cpu_thread *cpu; - bool has_waker = false; - bool target_le = slw_current_le; - - if (flags & OPAL_REINIT_CPUS_HILE_BE) - target_le = false; - if (flags & OPAL_REINIT_CPUS_HILE_LE) - target_le = true; - - prlog(PR_TRACE, "SLW Reinit from CPU PIR 0x%04x," - " HILE set to %s endian...\n", - this_cpu()->pir, - target_le ? "little" : "big"); - - /* Prepare chips/cores for rvwinkle */ - for_each_chip(chip) { - if (!chip->slw_base) { - log_simple_error(&e_info(OPAL_RC_SLW_INIT), - "SLW: Not found on chip %d\n", chip->id); - return OPAL_HARDWARE; - } - - slw_patch_scans(chip, target_le); - } - slw_current_le = target_le; - - /* XXX Save HIDs ? Or do that in head.S ... */ - - slw_patch_reset(); - - /* rvwinkle everybody and pick one to wake me once I rvwinkle myself */ - for_each_available_cpu(cpu) { - struct cpu_thread *master = NULL; - - if (cpu == this_cpu()) - continue; - - /* Pick up a waker for myself: it must not be a sibling of - * the current CPU and must be a thread 0 (so it gets to - * sync its timebase before doing time_wait_ms() - */ - if (!has_waker && !cpu_is_sibling(cpu, this_cpu()) && - cpu_is_thread0(cpu)) { - has_waker = true; - master = this_cpu(); - } - __cpu_queue_job(cpu, "slw_do_rvwinkle", - slw_do_rvwinkle, master, true); - - /* Wait for it to claim to be down */ - while(cpu->state != cpu_state_rvwinkle) - sync(); - } - - /* XXX Wait one second ! (should check xscom state ? ) */ - prlog(PR_TRACE, "SLW: Waiting one second...\n"); - time_wait_ms(1000); - prlog(PR_TRACE, "SLW: Done.\n"); - - for_each_chip(chip) { - struct cpu_thread *c; - uint64_t tmp; - for_each_available_core_in_chip(c, chip->id) { - xscom_read(chip->id, - XSCOM_ADDR_P8_EX_SLAVE(pir_to_core_id(c->pir), - EX_PM_IDLE_STATE_HISTORY_PHYP), - &tmp); - prlog(PR_DEBUG, "SLW: core %x:%x" - " history: 0x%016llx (mid)\n", - chip->id, pir_to_core_id(c->pir), tmp); - } - } - - - /* Wake everybody except on my core */ - for_each_cpu(cpu) { - if (cpu->state != cpu_state_rvwinkle || - cpu_is_sibling(cpu, this_cpu())) - continue; - icp_kick_cpu(cpu); - - /* Wait for it to claim to be back (XXX ADD TIMEOUT) */ - while(cpu->state != cpu_state_active) - sync(); - } - - /* Did we find a waker ? If we didn't, that means we had no - * other core in the system, we can't do it - */ - if (!has_waker) { - prlog(PR_TRACE, "SLW: No candidate waker, giving up !\n"); - return OPAL_HARDWARE; - } - - /* Our siblings are rvwinkling, and our waker is waiting for us - * so let's just go down now - */ - slw_do_rvwinkle(NULL); - - slw_unpatch_reset(); - - for_each_chip(chip) - slw_cleanup_chip(chip); - - prlog(PR_TRACE, "SLW Reinit complete !\n"); - - return OPAL_SUCCESS; -} - static void slw_patch_regs(struct proc_chip *chip) { struct cpu_thread *c; diff --git a/include/skiboot.h b/include/skiboot.h index f3378ec28..fa5323231 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -311,11 +311,6 @@ extern enum wakeup_engine_states wakeup_engine_state; extern bool has_deep_states; extern void nx_p9_rng_late_init(void); - - -/* SLW reinit function for switching core settings */ -extern int64_t slw_reinit(uint64_t flags); - /* Patch SPR in SLW image */ extern int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);