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Sun, 24 Jan 2021 19:58:12 -0500 (EST) From: Stewart Smith To: skiboot@lists.ozlabs.org Date: Sun, 24 Jan 2021 16:58:04 -0800 Message-Id: <20210125005807.3019715-6-stewart@flamingspork.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210125005807.3019715-1-stewart@flamingspork.com> References: <20210125005807.3019715-1-stewart@flamingspork.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 4/7] Move npu_set_fence_state() to phb_ops X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This lets us consider not building in npu.o Signed-off-by: Stewart Smith --- core/hmi.c | 2 +- hw/npu.c | 7 +++++-- include/npu.h | 1 - include/pci.h | 3 +++ 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/core/hmi.c b/core/hmi.c index 120fe4b5..ee4c168e 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -768,7 +768,7 @@ static void find_npu_checkstop_reason(int flat_chip_id, npu_fir_action0, npu_fir_action1); /* Set the NPU to fenced since it can't recover. */ - npu_set_fence_state(p, true); + phb->ops->set_fence_state(phb, true); /* Set up the HMI event */ hmi_evt->severity = OpalHMI_SEV_WARNING; diff --git a/hw/npu.c b/hw/npu.c index b747df2d..e31b4999 100644 --- a/hw/npu.c +++ b/hw/npu.c @@ -925,7 +925,9 @@ static int64_t npu_eeh_next_error(struct phb *phb, } /* For use in error injection and handling. */ -void npu_set_fence_state(struct npu *p, bool fence) { +static void npu_set_fence_state(struct phb *phb, bool fence) { + struct npu *p = phb_to_npu(phb); + p->fenced = fence; if (fence) @@ -968,7 +970,7 @@ static int64_t npu_err_inject(struct phb *phb, uint64_t pe_number, return OPAL_PARAMETER; } else if (type == 1) { /* Emulate fence mode. */ - npu_set_fence_state(p, true); + npu_set_fence_state(phb, true); } else { /* Cause a freeze with an invalid MMIO read. If the BAR is not * enabled, this will checkstop the machine. @@ -1012,6 +1014,7 @@ static const struct phb_ops npu_ops = { .get_diag_data2 = NULL, .set_capi_mode = NULL, .set_capp_recovery = NULL, + .set_fence_state = npu_set_fence_state, }; static void assign_mmio_bars(uint32_t gcid, uint32_t xscom, diff --git a/include/npu.h b/include/npu.h index 50cc9c9f..45818a28 100644 --- a/include/npu.h +++ b/include/npu.h @@ -153,7 +153,6 @@ int64_t npu_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf, uint32_t offset, uint32_t len, uint32_t *data, bool write); -void npu_set_fence_state(struct npu *p, bool fence); void npu_dev_procedure_reset(struct npu_dev *dev); #define NPUDBG(p, fmt, a...) prlog(PR_DEBUG, "NPU%d: " fmt, \ diff --git a/include/pci.h b/include/pci.h index eb23a6d9..05d02171 100644 --- a/include/pci.h +++ b/include/pci.h @@ -340,6 +340,9 @@ struct phb_ops { /* Get/set PBCQ Tunnel BAR register */ void (*get_tunnel_bar)(struct phb *phb, uint64_t *addr); int64_t (*set_tunnel_bar)(struct phb *phb, uint64_t addr); + + /* Currently only used by NPU HMI code */ + void (*set_fence_state)(struct phb *phb, bool fence); }; enum phb_type {