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[14.200.206.90]) by smtp.gmail.com with ESMTPSA id g4sm17909258pgg.75.2020.10.11.19.53.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Oct 2020 19:53:43 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Mon, 12 Oct 2020 13:53:10 +1100 Message-Id: <20201012025314.1070230-6-oohall@gmail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201012025314.1070230-1-oohall@gmail.com> References: <20201012025314.1070230-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 06/10] hw/p8-i2c: Print interrupt status per master X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Whether I2C interrupts work or not depends on the type of master. Currently we print a single message to indicate whether IRQs work or not, but this will be wrong if we have I2C interrupts on the host and we happen to probe a Centaur I2C master first. Fix this by adding a message to the per-master print indicating whether the master has an interrupt or not. Signed-off-by: Oliver O'Halloran --- hw/p8-i2c.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index 60bea868fda2..78f1e7e32932 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -1447,7 +1447,6 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) struct p8_i2c_master *master; struct list_head *chip_list; uint64_t ex_stat, default_timeout; - static bool irq_printed; int64_t rc; master = zalloc(sizeof(*master)); @@ -1496,8 +1495,11 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) init_timer(&master->recovery, p8_i2c_recover, master); init_timer(&master->sensor_cache, p8_i2c_enable_scache, master); - prlog(PR_INFO, "I2C: Chip %08x Eng. %d Clock %d Mhz\n", - master->chip_id, master->engine_id, lb_freq / 1000000); + master->irq_ok = p8_i2c_has_irqs(master); + + prlog(PR_INFO, "I2C: Chip %08x Eng. %d Clock %d Mhz %s\n", + master->chip_id, master->engine_id, lb_freq / 1000000, + master->irq_ok ? "" : "(no interrupt)"); /* Disable OCC cache during inits */ if (master->type == I2C_CENTAUR) { @@ -1526,14 +1528,6 @@ static void p8_i2c_init_one(struct dt_node *i2cm, enum p8_i2c_master_type type) list_head_init(&master->req_list); list_head_init(&master->ports); - /* Check if interrupt is usable */ - master->irq_ok = p8_i2c_has_irqs(master); - if (!irq_printed) { - irq_printed = true; - prlog(PR_INFO, "I2C: Interrupts %sfunctional\n", - master->irq_ok ? "" : "non-"); - } - /* Re-enable the sensor cache, we aren't touching HW anymore */ if (master->type == I2C_CENTAUR) centaur_enable_sensor_cache(master->chip_id);