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Wed, 26 Aug 2020 18:38:47 +0000 Received: from b03ledav001.gho.boulder.ibm.com (b03ledav001.gho.boulder.ibm.com [9.17.130.232]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 07QIch6q60031292 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 26 Aug 2020 18:38:43 GMT Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8AFED6E04C for ; Wed, 26 Aug 2020 18:38:46 +0000 (GMT) Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2CE756E04E for ; Wed, 26 Aug 2020 18:38:46 +0000 (GMT) Received: from alain.ibm.com (unknown [9.160.10.71]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP for ; Wed, 26 Aug 2020 18:38:46 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Wed, 26 Aug 2020 14:37:48 -0400 Message-Id: <20200826183749.143980-11-grimm@linux.ibm.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200826183749.143980-1-grimm@linux.ibm.com> References: <20200826183749.143980-1-grimm@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_10:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 phishscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 suspectscore=13 impostorscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008260134 Subject: [Skiboot] [PATCH v8 10/11] skiboot/imc: Disable IMC node when UV enabled X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan Don't create the IMC nodes when the ultravisor is enabled. Hypervisor IMC initialization requires access to HOMER and IMC scoms which are protected and only accessable via ultra calls. So, don't create them until the kernel supports the ultra calls. Signed-off-by: Madhavan Srinivasan [ grimm: move S bit check to beginning of function ] [ grimm: comments and commit message ] Signed-off-by: Ryan Grimm --- hw/imc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/imc.c b/hw/imc.c index 927fba0b..f6351225 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -527,6 +527,16 @@ void imc_init(void) struct dt_node *dev; int err_flag = -1; + /* + * If MSR(S) bit is set, HOMER and IMC scoms are only accessible via + * ultra call. The kernels lacks support, so don't create them. + * + * At this point uv_present can't be used since uv_init() + * is called much later, so check the MSR bit. + */ + if (is_msr_bit_set(MSR_S)) + return; + if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) { dev = dt_find_compatible_node(dt_root, NULL, "ibm,opal-in-memory-counters");